Abstract: A memory device includes a memory cell array, first and second memory cells, first and second read circuits, and first and second write circuits. The memory cell array includes first and second sub-arrays. The first memory cells are included in each of the first sub-arrays. The second memory cells are included in each of the second sub-arrays. The first and second read circuits are provided for reading data of the first and second memory cells, respectively. The first and second write circuits are provided for writing data to the first and second memory cells, respectively. An area of the first sub-array is different from an area of the second sub-array.

Abstract: A magnetoresistance memory device includes a first conductor, a first insulator covering a side surface of the first conductor, a second conductor on the first conductor that are substantially made of a non-magnetic non-nitrogen material. The device includes a variable resistance material, a third conductor, a first ferromagnetic layer, an insulating layer, and a second ferromagnetic layer. The third conductor, a fourth conductor on the second ferromagnetic layer, and a second insulator covering side surfaces of the first and second ferromagnetic layers and insulating layer are substantially made of a non-nitrogen material. A third insulator is on the second insulator.

Abstract: A memory device according to an embodiment includes a memory cell array, first and second memory cells, first and second read circuit, and first and second write circuit. The memory cell array includes first and second sub-arrays. The first memory cells is included in each of the first sub-arrays. The second memory cells is included in each of the second sub-arrays. The first and second read circuit are provided for reading data of the first and second memory cells, respectively. The first and second write circuit are provided for writing data to the first and second memory cells, respectively. An area of the first sub-array is different from an area of the second sub-array.

Abstract: A semiconductor memory device includes: a first memory cell and switching element coupled in series between a first and second interconnect; a second memory cell and switching element coupled in series between the first and a third interconnect; a third memory cell and switching element coupled in series between the first and a fourth interconnect; and a control circuit. The control circuit is configured to: in a first operation on the first memory cell, upon receipt of a first command, apply a third voltage between the first and second voltage to the third and fourth interconnect; and upon receipt of a second command, apply the first and third voltage to the fourth and third interconnect, respectively.

Abstract: A semiconductor memory device includes: a first memory cell and switching element coupled in series between a first and second interconnect; a second memory cell and switching element coupled in series between the first and a third interconnect; a third memory cell and switching element coupled in series between the first and a fourth interconnect; and a control circuit. The control circuit is configured to: in a first operation on the first memory cell, upon receipt of a first command, apply a third voltage between the first and second voltage to the third and fourth interconnect; and upon receipt of a second command, apply the first and third voltage to the fourth and third interconnect, respectively.

Abstract: A memory device includes a magnetoresistive element including first and second magnetic layers and a non-magnetic layer provided between the first and second magnetic layers. The memory device also includes a write circuit which controls a first writing setting magnetization of the first and second magnetic layers in a parallel state and a second writing setting the magnetization of the first and second magnetic layers in an antiparallel state, and applies a write current to the magnetoresistive element. A first write current in the first writing includes a first pulse and a second pulse added to the first pulse. A width of the second pulse is smaller than a width of the first pulse, and a current level of the second pulse is different from a current level of the first pulse.

Abstract: A magnetic storage device includes a first and a second stacked body including a first ferromagnetic body and a second ferromagnetic body, respectively. A first magnetoresistive effect element includes the first ferromagnetic body and a third ferromagnetic body with a first nonmagnetic body between the first and third ferromagnetic bodies. A second magnetoresistive effect element includes the first ferromagnetic body and a fourth ferromagnetic body with a second nonmagnetic body between the first and fourth ferromagnetic bodies. A third magnetoresistive effect element includes the second ferromagnetic body and a fifth ferromagnetic body with a third nonmagnetic body between the second and fifth ferromagnetic bodies. A fourth magnetoresistive effect element includes the second ferromagnetic body and a sixth ferromagnetic body with a fourth nonmagnetic body between the second and sixth ferromagnetic bodies. The third and fourth ferromagnetic bodies are between the first and second stacked bodies.

Abstract: A magnetic storage device includes a first and a second stacked body including a first ferromagnetic body and a second ferromagnetic body, respectively. A first magnetoresistive effect element includes the first ferromagnetic body and a third ferromagnetic body with a first nonmagnetic body between the first and third ferromagnetic bodies. A second magnetoresistive effect element includes the first ferromagnetic body and a fourth ferromagnetic body with a second nonmagnetic body between the first and fourth ferromagnetic bodies. A third magnetoresistive effect element includes the second ferromagnetic body and a fifth ferromagnetic body with a third nonmagnetic body between the second and fifth ferromagnetic bodies. A fourth magnetoresistive effect element includes the second ferromagnetic body and a sixth ferromagnetic body with a fourth nonmagnetic body between the second and sixth ferromagnetic bodies. The third and fourth ferromagnetic bodies are between the first and second stacked bodies.

Abstract: According to one embodiment, a magnetic memory device includes a first magnetic layer having a variable magnetization direction, a first non-magnetic layer provided on the first magnetic layer, and a second magnetic layer provided on the first magnetic layer and having a fixed magnetization direction and provided on the first magnetic layer. The second magnetic layer includes a non-magnetic metal including at least one of Mo (molybdenum), Ta (tantalum), W (tungsten), Hf (hafnium), Nb (niobium) and Ti (titanium).

Abstract: A memory device includes a magnetoresistive element including first and second magnetic layers and a non-magnetic layer provided between the first and second magnetic layers. The memory device also includes a write circuit which controls a first writing setting magnetization of the first and second magnetic layers in a parallel state and a second writing setting the magnetization of the first and second magnetic layers in an antiparallel state, and applies a write current to the magnetoresistive element. A first write current in the first writing includes a first pulse and a second pulse added to the first pulse. A width of the second pulse is smaller than a width of the first pulse, and a scurrent level of the second pulse is different from a current level of the first pulse.

Abstract: According to one embodiment, a memory device includes: a magnetoresistive element including first and second magnetic layers and a non-magnetic layer provided between the first and second magnetic layers; and a write circuit which controls a first writing setting magnetization of the first and second magnetic layers in a parallel state and a second writing setting the magnetization of the first and second magnetic layers in an antiparallel state, and applies a current pulse to the magnetoresistive element. A first pulse pattern used in the first writing is different from a second pulse pattern used in the second writing.

Abstract: According to an embodiment, a resistance change memory includes a semiconductor substrate, a transistor having a control terminal, a first terminal and a second terminal, the transistor provided on the semiconductor substrate, an insulating layer covering the transistor, a first conductive line connected to the first terminal and provided on the insulating layer, a second conductive line provided on the insulating layer, and a resistance change element connected between the second terminal and the second conductive line. The first conductive line has a width greater than a width of the second conductive line in a direction in which the first and second conductive lines are arranged.

Abstract: A magnetoresistive effect element according to one embodiment includes: a first magnetic layer; a nonmagnetic layer; a second magnetic layer; a metal layer; and a third magnetic layer. An area of a bottom of the third magnetic layer is larger than an area of a top of the third magnetic layer. An angle between the top of the third magnetic layer and a side of the third magnetic layer is larger than an angle between a top of the second magnetic layer and a side of the second magnetic layer, or an angle between the bottom of the third magnetic layer and a side of the third magnetic layer is smaller than an angle between the bottom of the second magnetic layer and a side of the second magnetic layer.

Abstract: According to one embodiment, a magnetic memory device includes a first magnetic layer having a variable magnetization direction, a first non-magnetic layer provided on the first magnetic layer, and a second magnetic layer provided on the first magnetic layer and having a fixed magnetization direction and provided on the first magnetic layer. The second magnetic layer includes a non-magnetic metal including at least one of Mo (molybdenum), Ta (tantalum), W (tungsten), Hf (hafnium), Nb (niobium) and Ti (titanium).

Abstract: According to an embodiment, a resistance change memory includes a semiconductor substrate, a transistor having a control terminal, a first terminal and a second terminal, the transistor provided on the semiconductor substrate, an insulating layer covering the transistor, a first conductive line connected to the first terminal and provided on the insulating layer, a second conductive line provided on the insulating layer, and a resistance change element connected between the second terminal and the second conductive line. The first conductive line has a width greater than a width of the second conductive line in a direction in which the first and second conductive lines are arranged.

Abstract: According to one embodiment, a memory device includes: a magnetoresistive element including first and second magnetic layers and a non-magnetic layer provided between the first and second magnetic layers; and a write circuit which controls a first writing setting magnetization of the first and second magnetic layers in a parallel state and a second writing setting the magnetization of the first and second magnetic layers in an antiparallel state, and applies a current pulse to the magnetoresistive element. A first pulse pattern used in the first writing is different from a second pulse pattern used in the second writing.

Abstract: A magnetoresistive effect element according to one embodiment includes: a first magnetic layer; a nonmagnetic layer; a second magnetic layer; a metal layer; and a third magnetic layer. An area of a bottom of the third magnetic layer is larger than an area of a top of the third magnetic layer. An angle between the top of the third magnetic layer and a side of the third magnetic layer is larger than an angle between a top of the second magnetic layer and a side of the second magnetic layer, or an angle between the bottom of the third magnetic layer and a side of the third magnetic layer is smaller than an angle between the bottom of the second magnetic layer and a side of the second magnetic layer.

Abstract: According to one embodiment, a magnetic storage device includes a first and a second magnetoresistive effect element, which are disposed in an arrangement pattern including a plurality of arrangement areas, and in each of which a second ferromagnetic layer and a third ferromagnetic layer are antiferromagnetically coupled. A magnetization orientation of the third ferromagnetic layer of the first magnetoresistive effect element is antiparallel to a magnetization orientation of the third ferromagnetic layer of the second magnetoresistive effect element. The first magnetoresistive effect element is disposed in an arrangement area randomly positioned with respect to an arrangement area in which the second magnetoresistive effect element is disposed.

Abstract: According to one embodiment, a testing method of a memory device includes annealing the memory device, the memory device including a memory element; performing, after the annealing, to the memory element a process which sets a first magnetization orientation of a first ferromagnetic layer to be antiparallel to a second magnetization orientation of the second ferromagnetic layer; reading, after the performing of the process, data from the memory element; and determining the memory element as defective due to the second magnetization orientation being parallel to a third magnetization orientation of a third ferromagnetic layer, when data represented by the first magnetization orientation being antiparallel to the second magnetization orientation differs from the read data.

Abstract: According to one embodiment, a method for manufacturing a magnetic memory is disclosed. The method includes forming a magnetoresistive element on a substrate. The method further includes measuring an electrical characteristic of the magnetoresistive element, and applying a voltage to the magnetoresistive element which the electrical characteristic is measured.