Patents by Inventor Hisanori Misawa

Hisanori Misawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7339247
    Abstract: A method of manufacturing a semiconductor device is disclosed, which comprises setting a stencil mask above a substrate to be processed in confronting to the substrate, the stencil mask having an opening, and irradiating the substrate with charged particles through the opening of the stencil mask, while adjusting a potential difference between the stencil mask and the substrate depending on a value of a current flowing between the substrate and the stencil mask.
    Type: Grant
    Filed: July 19, 2006
    Date of Patent: March 4, 2008
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takeshi Shibata, Hisanori Misawa, Kyoichi Suguro
  • Patent number: 7282725
    Abstract: A manufacturing apparatus of a semiconductor device is disclosed, which comprises an implantation source which applies particles or an electromagnetic wave into an implantation region of a semiconductor substrate in a ? direction shifted by an angle ? from a vertical direction of the semiconductor substrate, a first stencil mask disposed between the semiconductor substrate and the implantation source, the first stencil mask having a first opening corresponding in the ? direction to the implantation region, and a second stencil mask disposed between the first stencil mask and the implantation source, the second stencil mask having a second opening corresponding in the ? direction to the implantation region.
    Type: Grant
    Filed: November 22, 2005
    Date of Patent: October 16, 2007
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takeshi Shibata, Hisanori Misawa
  • Publication number: 20060263704
    Abstract: A method of manufacturing a semiconductor device is disclosed, which comprises setting a stencil mask above a substrate to be processed in confronting to the substrate, the stencil mask having an opening, and irradiating the substrate with charged particles through the opening of the stencil mask, while adjusting a potential difference between the stencil mask and the substrate depending on a value of a current flowing between the substrate and the stencil mask.
    Type: Application
    Filed: July 19, 2006
    Publication date: November 23, 2006
    Inventors: Takeshi Shibata, Hisanori Misawa, Kyoichi Suguro
  • Patent number: 7094612
    Abstract: A method of manufacturing a semiconductor device is disclosed, which comprises setting a stencil mask above a substrate to be processed in confronting to the substrate, the stencil mask having an opening, and irradiating the substrate with charged particles through the opening of the stencil mask, while adjusting a potential difference between the stencil mask and the substrate depending on a value of a current flowing between the substrate and the stencil mask.
    Type: Grant
    Filed: December 23, 2003
    Date of Patent: August 22, 2006
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takeshi Shibata, Hisanori Misawa, Kyoichi Suguro
  • Patent number: 7034318
    Abstract: A manufacturing apparatus of a semiconductor device is disclosed, which comprises an implantation source which applies particles or an electromagnetic wave into an implantation region of a semiconductor substrate in a ? direction shifted by an angle ? from a vertical direction of the semiconductor substrate, a first stencil mask disposed between the semiconductor substrate and the implantation source, the first stencil mask having a first opening corresponding in the ? direction to the implantation region, and a second stencil mask disposed between the first stencil mask and the implantation source, the second stencil mask having a second opening corresponding in the ? direction to the implantation region.
    Type: Grant
    Filed: December 18, 2003
    Date of Patent: April 25, 2006
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takeshi Shibata, Hisanori Misawa
  • Publication number: 20060071183
    Abstract: A manufacturing apparatus of a semiconductor device is disclosed, which comprises an implantation source which applies particles or an electromagnetic wave into an implantation region of a semiconductor substrate in a ? direction shifted by an angle ? from a vertical direction of the semiconductor substrate, a first stencil mask disposed between the semiconductor substrate and the implantation source, the first stencil mask having a first opening corresponding in the ? direction to the implantation region, and a second stencil mask disposed between the first stencil mask and the implantation source, the second stencil mask having a second opening corresponding in the ? direction to the implantation region.
    Type: Application
    Filed: November 22, 2005
    Publication date: April 6, 2006
    Inventors: Takeshi Shibata, Hisanori Misawa
  • Publication number: 20040185644
    Abstract: A manufacturing apparatus of a semiconductor device is disclosed, which comprises an implantation source which applies particles or an electromagnetic wave into an implantation region of a semiconductor substrate in a &thgr; direction shifted by an angle &thgr; from a vertical direction of the semiconductor substrate, a first stencil mask disposed between the semiconductor substrate and the implantation source, the first stencil mask having a first opening corresponding in the &thgr; direction to the implantation region, and a second stencil mask disposed between the first stencil mask and the implantation source, the second stencil mask having a second opening corresponding in the &thgr; direction to the implantation region.
    Type: Application
    Filed: December 18, 2003
    Publication date: September 23, 2004
    Inventors: Takeshi Shibata, Hisanori Misawa
  • Publication number: 20040137759
    Abstract: A method of manufacturing a semiconductor device is disclosed, which comprises setting a stencil mask above a substrate to be processed in confronting to the substrate, the stencil mask having an opening, and irradiating the substrate with charged particles through the opening of the stencil mask, while adjusting a potential difference between the stencil mask and the substrate depending on a value of a current flowing between the substrate and the stencil mask.
    Type: Application
    Filed: December 23, 2003
    Publication date: July 15, 2004
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Takeshi Shibata, Hisanori Misawa, Kyoichi Suguro
  • Patent number: 5179433
    Abstract: A breakdown evaluating test element insert an oxide film having thin thick portion and formed on a silicon wafer and a polysilicon film formed on the oxide film, in such a way that a capacitor is formed between the silicon wafer and the polysilicon film with the oxide film as dielectric. The area of the polysilicon film is made larger than that of the thin portion of the oxide film so that only the thin portion thereof is brought into breakdown at a predetermined probability by an electric field strength generated at the thin portion when an electric field is applied to the wafer and when no electron shower is used (no breakdown prevention countermeasure is taken) during ion implantation, for instance. Therefore, the effect of the electron shower can be confirmed by checking the resistivity of the thin oxide film portion after the wafer has been ion-implanted by using an electron shower.
    Type: Grant
    Filed: June 12, 1991
    Date of Patent: January 12, 1993
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hisanori Misawa, Masakazu Shiozaki
  • Patent number: 4783597
    Abstract: An ion implant apparatus which forms ions from an ion source into an ion beam to implant the ions into a target to be ion-implanted through an ion beam introduction tube. The ion implant apparatus comprises: radiation means for radiating an electron beam, the radiating means fixed on the ion beam introduction tube; and a target for being radiated by an electron beam, said target reflecting the electron beam to generate a reflectance beam, the electron beam causing a secondary electron beam to be emitted from the electron beam target, the electron beam target being formed so as to prevent the reflectance beam and the secondary electron beam from being directly radiated on the target to be ion-implanted. The apparatus can keep high energy electrons from the surface of a wafer thereby to prevent the wafer from being charged negatively, and can trap the high energy electrons in the measuring system thereby to decrease errors in measuring a number of dopant atoms.
    Type: Grant
    Filed: October 29, 1986
    Date of Patent: November 8, 1988
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hisanori Misawa, Hidetaro Nishimura, Takaya Tsujimaru, Shuji Kikuchi, Nobuyuki Abe, Kouichi Mori