Abstract: A shield casing of an image display apparatus including a casing which covers other than a front surface of an image display device having an electromagnetic wave emitter and shielding the electromagnetic waves, a protection panel on which a conductive film is laminated, and a mounting device which is in contact with the conductive film and attaches the protection panel to the casing, wherein the mounting device has an arm stretching toward a front side of the protection panel, a tip portion of the arm curves toward the protection panel and has a contact surface with the protection panel on an outer side surface of the tip portion, and the mounting device mounts the protection panel to the casing with the force more than supporting the protection panel.

Abstract: A shield casing of an image display apparatus including a casing which covers other than a front surface of an image display device having an electromagnetic wave emitter and shielding the electromagnetic waves, a protection panel on which a conductive film is laminated, and a mounting device which is in contact with the conductive film and attaches the protection panel to the casing, wherein the mounting device has an arm stretching toward a front side of the protection panel, a tip portion of the arm curves toward the protection panel and has a contact surface with the protection panel on an outer side surface of the tip portion, and the mounting device mounts the protection panel to the casing with the force more than supporting the protection panel.

Abstract: In a logic semiconductor integrated circuit, a memory-cell array having memory cells MC, word lines WL, pairs of bit lines BL and /BL, sense amplifiers SA-N and SA-P and gates TG are located in a DRAM forming area of a semiconductor substrate. A refresh counter is located in a logic forming area of the semiconductor substrate. The refresh counter is used for generating a refresh-time word-line select signal for selecting one of the word lines WL when the memory cells MC are refreshed. Input/output buffers for inputting and outputting data transmitted through input/output lines are also located in the logic forming area of the semiconductor substrate. In addition, logic circuits such as inverters, AND gates, OR gates, NAND gates, NOR gates and flip-flops are located in the logic forming area of the semiconductor substrate as well. A logic semiconductor integrated circuit device having an embedded DRAM with a high degree of freedom in laying out components is provided by the invention.