Patents by Inventor Hisanori Yoshimizu

Hisanori Yoshimizu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20150257284
    Abstract: A method for bending back a rigid printed wiring board with a flexible portion includes: forming a preparation substrate on a surface of a prepreg made of thermosetting resin, the preparation substrate including a conducting layer made of a conductive material; laminating the plurality of preparation substrates; thermally hardening the thermosetting resin so as to integrate the plurality of laminated preparation substrates as an intermediate substrate while heating and pressing together the plurality of preparation substrates; cutting an insulating layer formed by thermally hardening the thermosetting resin in a lamination direction of the preparation substrate so as to form a flexible portion, the flexible portion being thinly formed across opposed both edges of the intermediate substrate to form a complete substrate; bending the flexible portion; bending-back the flexible portion; and dehydrating by raising a temperature of the bent flexible portion before bending-back the flexible portion.
    Type: Application
    Filed: March 7, 2014
    Publication date: September 10, 2015
    Applicant: MEIKO ELECTRONICS CO., LTD.
    Inventors: Mitsuaki Toda, Kazuo Shishime, Hisanori Yoshimizu
  • Patent number: 6704208
    Abstract: A manufacturing method of a printed circuit board is composed of a first process of forming a pattern of lower electrode 4a at a specific portion on a substrate 2 in which a capacitor element 16 is formed, a second process of forming a capacitor insulative layer 6 that is constituted by a paste material having high permittivity selectively at a position that corresponds to the lower electrode 4a, a third process of forming an interlayer insulative film 8 having low permittivity all over the entire surface of the substrate 2 including the capacitor insulative layer 6, a fourth process of exposing the capacitor insulative layer 6 by grinding the surface of the interlayer insulative film 8 so as to be flat, and a fifth process of forming a capacitor element 16 by forming a pattern of upper electrode on the surface of the capacitor insulative layer 6. Accordingly, the printed circuit board is excellent in mechanical strength, low in manufacturing cost and high in reliability and capacitance accuracy.
    Type: Grant
    Filed: September 11, 2002
    Date of Patent: March 9, 2004
    Assignee: Victor Company of Japan, Ltd.
    Inventors: Koichi Kamiyama, Hisanori Yoshimizu, Shigeru Michiwaki
  • Publication number: 20030063443
    Abstract: A manufacturing method of a printed circuit board is composed of a first process of forming a pattern of lower electrode 4a at a specific portion on a substrate 2 in which a capacitor element 16 is formed, a second process of forming a capacitor insulative layer 6 that is constituted by a paste material having high permittivity selectively at a position that corresponds to the lower electrode 4a, a third process of forming an interlayer insulative film 8 having low permittivity all over the entire surface of the substrate 2 including the capacitor insulative layer 6, a fourth process of exposing the capacitor insulative layer 6 by grinding the surface of the interlayer insulative film 8 so as to be flat, and a fifth process of forming a capacitor element 16 by forming a pattern of upper electrode on the surface of the capacitor insulative layer 6. Accordingly, the printed circuit board is excellent in mechanical strength, low in manufacturing cost and high in reliability and capacitance accuracy.
    Type: Application
    Filed: September 11, 2002
    Publication date: April 3, 2003
    Inventors: Koichi Kamiyama, Hisanori Yoshimizu, Shigeru Michiwaki
  • Publication number: 20020171530
    Abstract: The present invention provides a thin film capacitance element having minimal deviation of capacitance value in a high accuracy formed on a printed circuit board (core material). The thin film capacitance element formed on a printed circuit board is composed of a lower electrode layer formed on the printed circuit board through an insulation layer, a dielectric layer formed on the lower electrode layer, an upper electrode layer formed on the dielectric layer and an electric pad for leading out the lower electrode layer, wherein the lower electrode layer is longer than the upper electrode layer in the horizontal direction and connected to the electric pad for leading out the lower electrode layer outside, and wherein the top surface of the upper electrode layer and the top surface of the electric pad for leading out the lower electrode layer are formed substantially in the same height.
    Type: Application
    Filed: March 28, 2002
    Publication date: November 21, 2002
    Applicant: VICTOR COMPANY OF JAPAN, LIMITED
    Inventors: Motoshi Shindoh, Shigeru Michiwaki, Koichi Kamiyama, Hisanori Yoshimizu
  • Patent number: 5155646
    Abstract: A thin-film magnetic head for magnetic recording and reproducing apparatus includes a lower insulating layer deposited on a substrate and including a lower magnetic core, an intermediate insulating layer deposited on the lower insulating layer and including front and rear intermediate magnetic cores, and an upper insulating layer deposited on the intermediate insulating layer and including an upper magnetic core. The magnetic cores make up a magnetic circuit which has a magnetic gap defined between the lower magnetic core and the front intermediate magnetic core or between the front intermediate magnetic core and the upper magnetic core. A multiturn coil is embedded in the intermediate insulating layer to surround the rear intermediate magnetic core. The lower, intermediate, and upper insulating layers have respective flat surfaces including respective surfaces of the lower, intermediate, and upper magnetic cores.
    Type: Grant
    Filed: July 25, 1990
    Date of Patent: October 13, 1992
    Assignee: Victor Company of Japan, Ltd.
    Inventors: Wataru Fujisawa, Shuji Orihara, Takaharu Nishino, Hisanori Yoshimizu