Abstract: A memory device includes: a plurality of word lines and bit lines specifying addresses to be accessed; and a plurality of memory cells of consecutive addresses arranged to correspond to each of the word lines. The plurality of memory cells of the consecutive addresses are accessible in parallel by the plurality of bit lines each corresponding to one of the memory cells. Among the plurality of word lines, a first word line and a second word line that specifies an address next to that of the first word line have an overlapping address range, and a first memory cell connected to the first word line and a second memory cell connected to the second word line are assigned in dual fashion to a same address.

Abstract: A memory device includes: a plurality of word lines and bit lines specifying addresses to be accessed; and a plurality of memory cells of consecutive addresses arranged to correspond to each of the word lines. The plurality of memory cells of the consecutive addresses are accessible in parallel by the plurality of bit lines each corresponding to one of the memory cells. Among the plurality of word lines, a first word line and a second word line that specifies an address next to that of the first word line have an overlapping address range, and a first memory cell connected to the first word line and a second memory cell connected to the second word line are assigned in dual fashion to a same address.

Abstract: A semiconductor device formed on a semiconductor chip includes a signal processing unit composed of a plurality of signal processing cells arranged side by side in a horizontal direction, and a plurality of input/output cells each connected to a corresponding one of the signal processing cells in a one-to-one relation. The signal processing unit is located near to one corner of the semiconductor chip, and the input/output cells are uniformly distributed and located along two sides defining the above mentioned corner. Each of the signal processing cells is configured to make it possible that a wiring conductor connecting between the signal processing cell and a corresponding one of the input/output cells is taken out either in an upward vertical direction or in a downward vertical direction from the signal processing cell, in accordance with the side of the semiconductor chip along which the corresponding input/output cell is located.

Abstract: A semiconductor device formed on a semiconductor chip includes a signal processing unit composed of a plurality of signal processing cells arranged side by side in a horizontal direction, and a plurality of input/output cells each connected to a corresponding one of the signal processing cells in a one-to-one relation. The signal processing unit is located near to one corner of the semiconductor chip, and the input/output cells are uniformly distributed and located along two sides defining the above mentioned corner. Each of the signal processing cells is configured to make it possible that a wiring conductor connecting between the signal processing cell and a corresponding one of the input/output cells is taken out either in an upward vertical direction or in a downward vertical direction from the signal processing cell, in accordance with the side of the semiconductor chip along which the corresponding input/output cell is located.

Abstract: A semiconductor integrated circuit has a clock input buffer, a set of clock drivers, an input buffer, an input latch, an output latch, and a three-state buffer. The clock input buffer produces a first intermediate clock signal in phase with an external clock signal and a second intermediate clock signal out of phase with the external clock signal. With the first intermediate clock signal applied, the set of clock drivers produce non-overlapping two internal clock signals, namely, a first internal clock signal in phase with the external clock signal and a second internal clock signal out of phase with the external clock signal. The input latch is controlled by either the first internal clock signal or the second internal clock signal and latches an output of the input buffer connected to an input/output terminal. The output latch is controlled by the second intermediate clock signal and the latch control signal and latches a signal to be outputted.

Abstract: A method of acceleration testing of reliability of an LSI adopting a microprogram is realized simply. In a test mode, a microaddress is progressively incremented "1" by "1" and data processing within the LSI is executed in accordance with a microcode read out from a control memory based on the microaddress. As for a command decoder and an address generator, external data terminals are clamped to a voltage source or to a ground to permit a specific command to be fetched by the LSI under test. In this way, a majority of internal gates within the LSI are activated while the acceleration test is being conducted on the LSI.

Abstract: A microprocessor having a multi-stage pipeline structure, comprises: a status flip-flop having its output changing when the instruction code of a predetermined instruction is decoded in the microprocessor; a circuit for outputting the output of the status flip-flop in synchronism with the output timing of an address for the bus cycle period of the microprocessor; and a circuit for sequentially storing the information, which appears at the input/output terminals of the microprocessor, as time-series data outside of the microprocessor. The time-series data is edited by discriminating the bus cycle of the microprocessor belongs to the bus cycle following an instruction on or before the predetermined instruction for changing the output of the status flip-flop or the bus cycle following an instruction on or after the predetermined instruction, with reference to the information outputted from the status flip-flop inside of the microprocessor to the outside of the same.

Abstract: An information processing apparatus with an instruction prefetch unit is disclosed, in which a CPU operation can be stopped at a desired address in response to a break signal. The instruction prefetch unit has an instruction prefetch circuit storing an instruction and an indication register storing the break signal. A read operation and a write operation of the indication register are executed together with those of the instruction prefetch circuit. Thus, a break point can be set a desired address by using the indication register, and the break operation can be correctly preformed without the need for complex hardware.