Abstract: A semiconductor device includes a semiconductor part including first to fifth layers; an electrode on a front surface of the semiconductor part; first and second control electrodes between the semiconductor part and the electrode. The first layer includes first and second portions alternately arranged along the front surface of the semiconductor part. The second layer is positioned between the first and second portions of the first layer. The first and second control electrodes are placed at boundaries of the first and second portions and the second layer, respectively. The third layer is provided between the second electrode and the first and second portions of the first layer. The fourth and fifth layers are selectively provided between the third layer and the second electrode. The first control electrode is opposed to the first, third and fourth layers. The second control electrode is opposed to the first, third and fifth layers.

Abstract: A semiconductor device includes a semiconductor part including first to fifth layers; an electrode on a front surface of the semiconductor part; first and second control electrodes between the semiconductor part and the electrode. The first layer includes first and second portions alternately arranged along the front surface of the semiconductor part. The second layer is positioned between the first and second portions of the first layer. The first and second control electrodes are placed at boundaries of the first and second portions and the second layer, respectively. The third layer is provided between the second electrode and the first and second portions of the first layer. The fourth and fifth layers are selectively provided between the third layer and the second electrode. The first control electrode is opposed to the first, third and fourth layers. The second control electrode is opposed to the first, third and fifth layers.

Abstract: According to one embodiment, a semiconductor device includes first and second electrodes, first, second, third, fourth, fifth, sixth and seventh semiconductor regions, and a gate electrode. The first semiconductor region is provided on the first electrode. The second semiconductor region is provided on a portion of the first semiconductor region. The third semiconductor region is provided on another portion of the first semiconductor region. The fourth semiconductor region is provided in at least a portion between the first and third semiconductor regions. The fifth semiconductor region is provided between the first and fourth semiconductor regions. The sixth semiconductor region is provided on the third semiconductor region. The seventh semiconductor region is provided selectively on the sixth semiconductor region. The gate electrode opposes the second, sixth, and seventh semiconductor regions. The second electrode is provided on the sixth and seventh semiconductor regions.

Abstract: A semiconductor device includes a semiconductor body, first and second electrodes, and a control electrode. The semiconductor body includes first to fourth semiconductor layers. The first electrode is provided on a front surface of the semiconductor body. The second electrode is provided on a back surface of the semiconductor body. The control electrode is provided between the semiconductor body and the first electrode. The second semiconductor layer is positioned between a portion and other portion of the first semiconductor layer in a first direction directed along the front surface. The third semiconductor layer contacts the portion of first semiconductor layer and the second semiconductor layer. The third semiconductor layer includes a first end portion positioned in the portion of the first semiconductor layer and a second end portion positioned in the second semiconductor layer. The fourth semiconductor layer is selectively provided in the second end portion.

Abstract: A semiconductor device of an embodiment includes a semiconductor layer having first and second plane, a first semiconductor region of a first conductivity type, second semiconductor regions of a second conductivity type between the first semiconductor region and the first plane, third semiconductor regions of a first conductivity type provided between the first semiconductor region and the first plane and provided between the second semiconductor regions, a fourth semiconductor region provided between the second semiconductor regions and the first plane, and having a higher second conductivity-type impurity concentration than the second semiconductor regions, a fifth semiconductor region of a first conductivity type between the fourth semiconductor region and the first plane, a sixth semiconductor region provided between the second semiconductor regions and the fourth semiconductor region, and having a higher electric resistance per unit depth than the second semiconductor regions, a gate electrode, and a gat

Abstract: A semiconductor device includes a semiconductor body, first to third electrodes provided on the semiconductor body, and a control electrode. The control electrode is provided between the semiconductor body and the first electrode. The semiconductor body includes first to sixth layers. The second layer of a second conductivity type is selectively provided between the first layer of a first conductivity type and the first electrode. The third layer of the first conductivity type is selectively provided between the second layer and the first electrode. The fourth layer of the second conductivity type is provided between the first layer and the second and third electrodes. The fifth layer of the first conductivity type is selectively provided in the fourth layer and electrically connected to the first electrode. The sixth layer of the first conductivity type is provided in the fourth layer, and electrically connected to the third electrode.

Abstract: According to one embodiment, a semiconductor device includes first and second electrodes, first, second, third, fourth, fifth, sixth and seventh semiconductor regions, and a gate electrode. The first semiconductor region is provided on the first electrode. The second semiconductor region is provided on a portion of the first semiconductor region. The third semiconductor region is provided on another portion of the first semiconductor region. The fourth semiconductor region is provided in at least a portion between the first and third semiconductor regions. The fifth semiconductor region is provided between the first and fourth semiconductor regions. The sixth semiconductor region is provided on the third semiconductor region. The seventh semiconductor region is provided selectively on the sixth semiconductor region. The gate electrode opposes the second, sixth, and seventh semiconductor regions. The second electrode is provided on the sixth and seventh semiconductor regions.

Abstract: A semiconductor device includes a semiconductor body, first to third electrodes provided on the semiconductor body, and a control electrode. The control electrode is provided between the semiconductor body and the first electrode. The semiconductor body includes first to sixth layers. The second layer of a second conductivity type is selectively provided between the first layer of a first conductivity type and the first electrode. The third layer of the first conductivity type is selectively provided between the second layer and the first electrode. The fourth layer of the second conductivity type is provided between the first layer and the second and third electrodes. The fifth layer of the first conductivity type is selectively provided in the fourth layer and electrically connected to the first electrode. The sixth layer of the first conductivity type is provided in the fourth layer, and electrically connected to the third electrode.

Abstract: A semiconductor device includes a semiconductor body including a first semiconductor layer of a first conductivity type and a second semiconductor layer of a second conductivity type. The first and second semiconductor layers are alternately arranged in a first direction along a front surface of the semiconductor body, and each include multiple portions arranged in a second direction directed from a back surface toward the front surface of the semiconductor body. The first and second semiconductor layers are configured such that, in an active region, a large/small relationship between amounts of the first conductivity type impurity and the second conductivity type impurity in the portions positioned at the same level in the second direction reverses at a center in the second direction of the second semiconductor layer, and in the terminal region, the large/small relationship reverses alternately in the portions arranged in the second direction.

Abstract: A semiconductor device includes a semiconductor body, first and second electrodes, and a control electrode. The semiconductor body includes first to fourth semiconductor layers. The first electrode is provided on a front surface of the semiconductor body. The second electrode is provided on a back surface of the semiconductor body. The control electrode is provided between the semiconductor body and the first electrode. The second semiconductor layer is positioned between a portion and other portion of the first semiconductor layer in a first direction directed along the front surface. The third semiconductor layer contacts the portion of first semiconductor layer and the second semiconductor layer. The third semiconductor layer includes a first end portion positioned in the portion of the first semiconductor layer and a second end portion positioned in the second semiconductor layer. The fourth semiconductor layer is selectively provided in the second end portion.

Abstract: A semiconductor device of an embodiment includes a semiconductor layer having a first plane and a second plane, a first semiconductor region of a first conductivity type, a second semiconductor region and a third semiconductor region of a second conductivity type, the first semiconductor region interposed between the third semiconductor region and the second semiconductor region, a first well region of a first conductivity type, a second well region of a first conductivity type separated from the first well region, a first contact region of a first conductivity type, a second contact region of a first conductivity type, a gate electrode provided on the first semiconductor region between the first well region and the second well region, a source electrode having a first region in contact with the first contact region and a second region in contact with the second contact region, and a drain electrode.

Abstract: A semiconductor device of an embodiment includes a semiconductor layer having a first plane and a second plane, a first semiconductor region of a first conductivity type, a second semiconductor region and a third semiconductor region of a second conductivity type, the first semiconductor region interposed between the third semiconductor region and the second semiconductor region, a first well region of a first conductivity type, a second well region of a first conductivity type separated from the first well region, a first contact region of a first conductivity type, a second contact region of a first conductivity type, a gate electrode provided on the first semiconductor region between the first well region and the second well region, a source electrode having a first region in contact with the first contact region and a second region in contact with the second contact region, and a drain electrode.

Abstract: A semiconductor device of an embodiment includes a semiconductor layer having first and second plane, a first semiconductor region of a first conductivity type, second semiconductor regions of a second conductivity type between the first semiconductor region and the first plane, third semiconductor regions of a first conductivity type provided between the first semiconductor region and the first plane and provided between the second semiconductor regions, a fourth semiconductor region provided between the second semiconductor regions and the first plane, and having a higher second conductivity-type impurity concentration than the second semiconductor regions, a fifth semiconductor region of a first conductivity type between the fourth semiconductor region and the first plane, a sixth semiconductor region provided between the second semiconductor regions and the fourth semiconductor region, and having a higher electric resistance per unit depth than the second semiconductor regions, a gate electrode, and a gat

Abstract: A semiconductor device includes a first conductivity type first semiconductor region, a second conductivity type second semiconductor region, a second conductivity type third semiconductor region, a first conductivity type fourth semiconductor region, a gate insulating portion, a gate electrode, and first and second electrodes. The first semiconductor region includes first and second portions. The second semiconductor region includes third and fourth portions. The gate electrode is on the gate insulating portion and over the first semiconductor region and a portion of the third semiconductor region. The first electrode is on, and electrically connected to, the fourth semiconductor region. The second electrode is over the first portion, the third portion, and the gate electrode, and spaced from the first electrode.

Abstract: A semiconductor device includes a first conductivity type first semiconductor region, a second conductivity type second semiconductor region, a second conductivity type third semiconductor region, a first conductivity type fourth semiconductor region, a gate insulating portion, a gate electrode, and first and second electrodes. The first semiconductor region includes first and second portions. The second semiconductor region includes third and fourth portions. The gate electrode is on the gate insulating portion and over the first semiconductor region and a portion of the third semiconductor region. The first electrode is on, and electrically connected to, the fourth semiconductor region. The second electrode is over the first portion, the third portion, and the gate electrode, and spaced from the first electrode.

Abstract: The semiconductor apparatus according to the present invention includes: a second-conductivity-type first diffusion region formed on the semiconductor layer; a first-conductivity-type second diffusion region formed in the first diffusion region; a second-conductivity-type first high concentration diffusion region and a first-conductivity-type second high concentration diffusion region formed in the second diffusion region; a second-conductivity-type third high concentration diffusion region, separated by a given distance from the second diffusion region, in the first diffusion region; and a gate electrode formed above and between the first high concentration diffusion region and third high concentration diffusion region, with a gate insulation film interposed therebetween, where the gate electrode is formed overlapping the first high concentration diffusion region, and the gate electrode is electrically connected with the first high concentration diffusion region and second high concentration diffusion region

Abstract: A P type semiconductor substrate includes a P type body region, an N type drift region formed away from the P type body region in a direction parallel to a substrate surface, an N type drain region formed in a region separated by a field oxide film in the N type drift region so as to have a concentration higher than the N type drift region, an N type source region formed in the P type body region so as to have a concentration higher than the N type drift region. A P type buried diffusion region having a concentration higher than the N type drift region is formed of a plurality of parts each of which is connected to a part of the bottom surface of the P type body region and extends parallel to the substrate surface and its tip end reaches the inside of the drift region.

Abstract: To provide a semiconductor device and a method of making the same, the device being capable of preventing decrease in the withstanding voltage along the direction perpendicular to the source-drain direction and thereby improving the resistance to an overvoltage (overcurrent), the device includes: a p-type semiconductor substrate 201; an n-type diffusion region 202; a p-type body region 206, a p-type buried diffusion region 204, and an n-type drift region 207 within the n-type diffusion region 202; an n-type source region 208 and a p-type body contact region 209 within the p-type body region 206; an n-type drain region 210 within the n-type drift region 207; a gate insulating film above the p-type body region 206; and a gate electrode 211 above the gate insulating film, where the region 204 extends away from the region 206 farther than the farther edge of the gate electrode 211 is along a cross section perpendicular to the source-drain direction.

Abstract: The semiconductor apparatus according to the present invention includes: a second-conductivity-type first diffusion region formed on the semiconductor layer; a first-conductivity-type second diffusion region formed in the first diffusion region; a second-conductivity-type first high concentration diffusion region and a first-conductivity-type second high concentration diffusion region formed in the second diffusion region; a second-conductivity-type third high concentration diffusion region, separated by a given distance from the second diffusion region, in the first diffusion region; and a gate electrode formed above and between the first high concentration diffusion region and third high concentration diffusion region, with a gate insulation film interposed therebetween, where the gate electrode is formed overlapping the first high concentration diffusion region, and the gate electrode is electrically connected with the first high concentration diffusion region and second high concentration diffusion region

Abstract: Provided are a semiconductor device which can be manufactured at low cost and has a low on-resistance and a high withstand voltage, and its manufacturing method. The semiconductor device comprises an N-type well area formed on a P-type semiconductor substrate, a P-type body area formed within the well area, an N-type source area formed within the body area, an N-type drain area formed at a distance from the body area within the well area, a gate insulating film formed so as to overlay a part of the body area, a gate electrode formed on the gate insulating film and a P-type buried diffusion area which makes contact with the bottom of the body area and extends to an area beneath the drain area in a direction parallel to the surface of the semiconductor substrate within the well area.