Abstract: A semiconductor device, including a first semiconductor chip including a first substrate having a semiconductor larger in bandgap than silicon, the first semiconductor chip being formed with a first FET including a first gate electrode, a first source, and a first drain, a second semiconductor chip including a second substrate having a semiconductor larger in bandgap than silicon, the second semiconductor chip being formed with a second FET having a second gate electrode, a second source, and a second drain, and a third semiconductor chip including a third substrate having silicon, the third semiconductor chip being formed with a MOSFET including a third gate electrode, a third source, and a third drain. The first semiconductor chip and the second semiconductor chip are mounted over a first chip mounting section, and the third semiconductor chip is mounted over a second chip mounting section.

Abstract: A semiconductor device includes: a first-conductivity-type semiconductor substrate serving as a drain layer; a first-conductivity-type epitaxial layer formed on the semiconductor substrate; a first-conductivity-type source layer formed in a surface part of the epitaxial layer; two second-conductivity-type gate layers formed in the surface part of the epitaxial layer so as to sandwich the source layer; a first-conductivity-type channel forming layer formed so as to be sandwiched between the two gate layers, the first-conductivity-type channel forming layer being formed on an inner side of the source layer in the epitaxial layer; and an electrode connected to one of the drain layer, the source layer, and the gate layer. In the channel forming layer, two first-conductivity-type impurity layers each having a substantially predetermined width are formed adjacent to each other in a direction crossing a channel.

Abstract: A semiconductor device, including a first semiconductor chip including a first substrate having a semiconductor larger in bandgap than silicon, the first semiconductor chip being formed with a first FET including a first gate electrode, a first source, and a first drain, a second semiconductor chip including a second substrate having a semiconductor larger in bandgap than silicon, the second semiconductor chip being formed with a second FET having a second gate electrode, a second source, and a second drain, and a third semiconductor chip including a third substrate having silicon, the third semiconductor chip being formed with a MOSFET including a third gate electrode, a third source, and a third drain. The first semiconductor chip and the second semiconductor chip are mounted over a first chip mounting section, and the third semiconductor chip is mounted over a second chip mounting section.

Abstract: The manufacturing yield of a semiconductor device is improved. There is provided a semiconductor device of a cascode coupling system, which is equipped with a plurality of normally-on junction FETs using as a material, a substance larger in bandgap than silicon, and a normally-off MOSFET using silicon as a material. At this time, the semiconductor chip has a plurality of junction FET semiconductor chips (semiconductor chip CHP0 and semiconductor chip CHP1) formed with the junction FETs in a divided fashion, and a MOSFET semiconductor chip (semiconductor chip CHP2) formed with the MOSFET.

Abstract: A semiconductor device includes: a first-conductivity-type semiconductor substrate serving as a drain layer; a first-conductivity-type epitaxial layer formed on the semiconductor substrate; a first-conductivity-type source layer formed in a surface part of the epitaxial layer; two second-conductivity-type gate layers formed in the surface part of the epitaxial layer so as to sandwich the source layer; a first-conductivity-type channel forming layer formed so as to be sandwiched between the two gate layers, the first-conductivity-type channel forming layer being formed on an inner side of the source layer in the epitaxial layer; and an electrode connected to one of the drain layer, the source layer, and the gate layer. In the channel forming layer, two first-conductivity-type impurity layers each having a substantially predetermined width are formed adjacent to each other in a direction crossing a channel.

Abstract: The manufacturing yield of a semiconductor device is improved. There is provided a semiconductor device of a cascode coupling system, which is equipped with a plurality of normally-on junction FETs using as a material, a substance larger in bandgap than silicon, and a normally-off MOSFET using silicon as a material. At this time, the semiconductor chip has a plurality of junction FET semiconductor chips (semiconductor chip CHP0 and semiconductor chip CHP1) formed with the junction FETs in a divided fashion, and a MOSFET semiconductor chip (semiconductor chip CHP2) formed with the MOSFET.

Abstract: The manufacturing yield of a semiconductor device is improved. There is provided a semiconductor device of a cascode coupling system, which is equipped with a plurality of normally-on junction FETs using as a material, a substance larger in bandgap than silicon, and a normally-off MOSFET using silicon as a material. At this time, the semiconductor chip has a plurality of junction FET semiconductor chips (semiconductor chip CHP0 and semiconductor chip CHP1) formed with the junction FETs in a divided fashion, and a MOSFET semiconductor chip (semiconductor chip CHP2) formed with the MOSFET.

Abstract: In one aspect, a semiconductor device includes a semiconductor substrate; and a transistor element including a parallel structure of a first-conductivity-type drift region and a second-conductivity-type column region, and a second-conductivity-type base region, the transistor element being formed on the semiconductor substrate. An outer peripheral region located outside an element forming region has a parallel structure of a first-conductivity-type drift region and a second-conductivity-type column region, and a second-conductivity-type annular diffusion region which is formed at a side of the base region and which is spaced apart from the base region. An innermost end and a neighboring portion thereof of the annular diffusion region are located on the column region, and an outermost end of the annular diffusion region is located outside an outermost peripheral column region. A field insulating film that covers the annular diffusion region is stacked on the semiconductor layer in the outer peripheral region.

Abstract: In one aspect, a semiconductor device includes a semiconductor substrate; and a transistor element including a parallel structure of a first-conductivity-type drift region and a second-conductivity-type column region, and a second-conductivity-type base region, the transistor element being formed on the semiconductor substrate. An outer peripheral region located outside an element forming region has a parallel structure of a first-conductivity-type drift region and a second-conductivity-type column region, and a second-conductivity-type annular diffusion region which is formed at a side of the base region and which is spaced apart from the base region. An innermost end and a neighboring portion thereof of the annular diffusion region are located on the column region, and an outermost end of the annular diffusion region is located outside an outermost peripheral column region. A field insulating film that covers the annular diffusion region is stacked on the semiconductor layer in the outer peripheral region.

Abstract: A semiconductor device includes: a semiconductor layer of a first conductivity type; a base region of a second conductivity type formed on a surface of the semiconductor layer of the first conductivity type; a plurality of first column regions of the second conductivity type formed in a matrix fashion in the semiconductor layer when seen in a plan view; a trench gate formed in a grid fashion in the semiconductor layer so that each of the first column regions is surrounded by the trench gate when seen in a plan view, the trench gate penetrating through the base region to reach the semiconductor layer of the first conductivity type; and a plurality of second column regions of the second conductivity type selectively formed below each intersection of the grid of the trench gate except line section of the trench gate.