Patents by Inventor Hisao Kondoh

Hisao Kondoh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5292672
    Abstract: In the present invention, baneful influences such as the reduction of the threshold voltage due to the irradiation of an ionizing radiation such as an electron beam and a light ion beam are removed to practice the lifetime control of an IGBT with good controllability. Basically, the lifetime control without change in the threshold voltage is implemented by increasing the threshold voltage on or before irradiating the ionizing radiation so as to cancel the influence of each other. Further, the lifetime control without change in the threshold voltage is implemented with higher accuracy by irradiating a light ion beam from a rear main electrode side so as to cause crystal defects locally in a specific region in an epitaxial layer.
    Type: Grant
    Filed: April 1, 1992
    Date of Patent: March 8, 1994
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Hajime Akiyama, Hisao Kondoh
  • Patent number: 5182626
    Abstract: In the present invention, baneful influences such as the reduction of the threshold voltage due to the irradiation of an ionizing radiation such as an electron beam and a light ion beam are removed to practice the lifetime control of an IGBT with good controllability. Basically, the lifetime control without change in the threshold voltage is implemented by increasing the threshold voltage on or before irradiating the ionizing radiation so as to cancel the influence of each other. Further, the lifetime control without change in the threshold voltage is implemented with higher accuracy by irradiating a light ion beam from a rear main electrode side so as to cause crystal defects locally in a specific region in an epitaxial layer.
    Type: Grant
    Filed: June 26, 1990
    Date of Patent: January 26, 1993
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Hajime Akiyama, Hisao Kondoh
  • Patent number: 5027180
    Abstract: A double gate static induction thyristor comprises a semiconductor substrate, a first gate region formed at a first principal surface of the substrate, and a first semiconductor region of a first conduction type formed on the same first principal surface. A second gate region is formed at a second principal surface of the substrate, and a second semiconductor region of a second conduction type is formed on the same second principal surface. Gate electrodes are formed on the first and second gate regions, and main electrodes are formed on the first and second semiconductor regions, so that portions of the semiconductor regions surrounded by the gate regions form a current path between the main electrodes. Further, impurity is deeply diffused in portions of the first and second gate regions formed with the gate electrodes.
    Type: Grant
    Filed: October 18, 1989
    Date of Patent: June 25, 1991
    Assignee: Mitsubishi Electric Corporation
    Inventors: Jun-ichi Nishizawa, Hisao Kondoh
  • Patent number: 4990978
    Abstract: A semiconductor substrate is provided thereon with an insulated gate bipolar transistor which is a composite element of a pnpn thyristor and an N-channel MOS-FET. In order to monitor operating current of the insulated gate bipolar transistor, a monitor terminal is provided in addition to collector, emitter and gate terminals. The operating current of the insulated gate bipolar transistor is monitored through the monitor terminal to perform appropriate protective operation when the operating current reaches a critical region, thereby to prevent occurrence of a latch-up phenomenon.
    Type: Grant
    Filed: January 13, 1989
    Date of Patent: February 5, 1991
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Hisao Kondoh
  • Patent number: 4870028
    Abstract: A double gate static induction thyristor comprises an n.sup.- semiconductor substrate having first and second principal surfaces opposite to each other. An n.sup.- epitaxial semiconductor layer is formed on the first principal surface of the substrate, and a p.sup.- epitaxial semiconductor layer is formed on the second principal surface of the substrate. A cathode electrode is deposited on the surface of the n.sup.- epitaxial layer, and an anode electrode is deposited on the surface of the p.sup.- epitaxial layer. In addition, a first gate electrode is formed on the first principal surface of the substrate, and a second gate electrode is formed on the second principal surface of the substrate.
    Type: Grant
    Filed: March 13, 1989
    Date of Patent: September 26, 1989
    Assignee: Mitsubishi Electric Corporation
    Inventors: Jun-ichi Nishizawa, Hisao Kondoh
  • Patent number: 4837608
    Abstract: A double gate static induction thyristor comprises an n.sup.- semiconductor substrate having first and second principal surfaces opposite to each other. An n.sup.- epitaxial semiconductor layer is formed on the first principal surface of the substrate, and a p.sup.- epitaxial semiconductor layer is formed on the second principal surface of the substrate. A cathode electrode is deposited on the surface of the n.sup.- epitaxial layer, and an anode electrode is deposited on the surface of the p.sup.- epitaxial layer. In addition, a first gate electrode is formed on the first principal surface of the substrate, and a second gate electrode is formed on the second principal surface of the substrate.
    Type: Grant
    Filed: July 14, 1988
    Date of Patent: June 6, 1989
    Assignee: Mitsubishi Electric Corporation
    Inventors: Jun-ichi Nishizawa, Hisao Kondoh
  • Patent number: 4673961
    Abstract: A pressurized contact type double gate static induction thyristor comprising a semiconductor body located in a casing and having cathode electrodes and a first gate electrode at one principal surface side thereof and anode electrodes and a second gate electrode at the other principal surface side thereof. A first thermal expansion stress buffer plate is located in the casing to be in contact with the cathode electrode, and a second thermal expansion stress buffer plate is located at the other principal surface side of the semiconductor body. This second plate is composed of at least two metal members electrically insulated from each other and integrally bonded by an insulating material, one of the two metal members being in contact with the anode electrode and the other metal member being in contact with the second gate electrode.
    Type: Grant
    Filed: March 13, 1986
    Date of Patent: June 16, 1987
    Assignee: Research Development, Corporation of Japan
    Inventors: Jun-ichi Nishizawa, Hisao Kondoh