Abstract: A vector information processing apparatus has a CPU comprising a plurality of asynchronously operating units, a main memory for storing data, and a main memory controller for controlling the writing of data in the main memory. The main memory controller has a VSC address buffer for holding a storage address in the main memory for each element designated by a vector scatter instruction. The main memory controller is arranged to inhibit the outputting of a writing permission signal for the main memory which is generated according to a writing request for writing an element having a smaller element number, which has the same storage address as the storage address and which has not been processed in a sequence of element numbers, of writing requests for writing elements in the main memory which are issued respectively from the asynchronously operating units according to a vector scatter instruction.

Abstract: The parallel processing system includes a plurality of nodes which are interconnected over an interconnection network; wherein the parallel processing system divides a computer job into parallel jobs by a parent process performed by a computer arranged in the nodes, and the parallel jobs are processed by the plurality of child processes using the plurality of computers arranged in the plurality of nodes; and a transfer process through the interconnection network from a slow child process in the child processes is performed on a basis of priority over other transfer processes.

Abstract: A vector artchitecture processing unit according to the present invention comprises a vector scatter (VSC) address coincidence detection unit 3 that comprises registers in which an area start address and an area end address of an area specified by an area-specified vector scatter instruction are stored; and a circuit that checks if the addresses specified by the area-specified vector scatter instruction overlap with an address to be accessed by a memory access instruction following the area-specified vector scatter instruction, wherein an instruction issue control unit 1 comprises a hold control circuit that holds the following memory access instruction in response to an address conflict signal from the VSC address conflict detector.

Abstract: A vector information processing apparatus has a CPU comprising a plurality of asynchronously operating units, a main memory for storing data, and a main memory controller for controlling the writing of data in the main memory. The main memory controller has a VSC address buffer for holding a storage address in the main memory for each element designated by a vector scatter instruction. The main memory controller is arranged to inhibit the outputting of a writing permission signal for the main memory which is generated according to a writing request for writing an element having a smaller element number, which has the same storage address as the storage address and which has not been processed in a sequence of element numbers, of writing requests for writing elements in the main memory which are issued respectively from the asynchronously operating units according to a vector scatter instruction.

Abstract: A hardware arrangement for implementing synchronization control between multiple processors is disclosed. The hardware arrangement is provided with a plurality of communication registers which are arranged so as to store synchronization control data applied from the processors. A flag bit register generates a plurality of flag bits which are respectively assigned to a plurality of critical sections. Each of the flag bits indicates whether or not the corresponding critical section is available. In order to assure the mutual exclusion control, a flag bit access control register is provided which generates a plurality of control bits that are respectively assigned to the plurality of flag bits. The control bit is used to prevent two processors from using an identical critical section. A controller is provided so as to adequately control the above-mentioned registers.

Abstract: A vector artchitecture processing unit according to the present invention comprises a vector scatter (VSC) address coincidence detection unit 3 that comprises registers in which an area start address and an area end address of an area specified by an area-specified vector scatter instruction are stored; and a circuit that checks if the addresses specified by the area-specified vector scatter instruction overlap with an address to be accessed by a memory access instruction following the area-specified vector scatter instruction, wherein an instruction issue control unit 1 comprises a hold control circuit that holds the following memory access instruction in response to an address conflict signal from the VSC address conflict detector.

Abstract: In order to implement vector operation at a higher rate, a processor chip, which is provided with a vector unit in addition to a scalar unit, is prepared. A vector operation mode is first determined, among first and second modes, via which the vector operation is implemented under control of the processor chip. The determination of the vector operation mode is carried out in said process chip. Thereafter, the vector operation is implemented using the vector unit provided in the processor chip if the vector operation mode is the first mode. On the other hand, the vector operation is implemented using a vector unit, which is provided outside the processor chip, if the vector operation mode is the second mode.