Patents by Inventor Hisao Nagayama

Hisao Nagayama has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8209594
    Abstract: A receiving device including: a receiver receiving two frames, each including substantially same data attached thereto with a data error detection code, a frame error detection code, and safety flag information indicating a safety function or not, respectively; a first detector connected to the receiver for performing error detection of the frames by use of the frame error detection code, respectively; a second detector connected to the receiver for performing error detection of the data by use of the data error detection code, respectively; and a Direct Memory Access Controller (DMAC) connected to the first and second detectors for outputting one among the data included in the two frames under a condition of the safety function in the two frames when no error is detected in the frame and data error detections.
    Type: Grant
    Filed: October 8, 2010
    Date of Patent: June 26, 2012
    Assignees: Hitachi, Ltd., Hitachi Information & Control Solutions, Ltd.
    Inventors: Akihiro Onozuka, Masakazu Ishikawa, Masamitsu Kobayashi, Takashi Umehara, Shin Kokura, Hiromichi Endoh, Satoru Funaki, Hisao Nagayama, Masahiro Shiraishi, Akira Bando, Eiji Kobayashi, Yasuyuki Furuta, Naoya Mashiko
  • Patent number: 8161362
    Abstract: Processed results are received when processors make compatible computations on data of a common object. A computation command signal is generated and fed to the processors in response to a start signal from any one of the processors so that the processors can make computations with different operation timings. Then, the results of the computations made by the processors are compared with each other. Thus, apparatus capable of small size, high performance and safety at the same time can be achieved by the above construction using the processors.
    Type: Grant
    Filed: June 7, 2006
    Date of Patent: April 17, 2012
    Assignees: Hitachi, Ltd., Hitachi Information & Control Solutions, Ltd.
    Inventors: Akira Bando, Shin Kokura, Takashi Umehara, Masamitsu Kobayashi, Hisao Nagayama, Naoya Mashiko, Masakazu Ishikawa, Masahiro Shiraishi, Akihiro Onozuka, Hiromichi Endoh, Tsutomu Yamada, Satoru Funaki
  • Publication number: 20110214125
    Abstract: An input/output control apparatus including: a unit that controls input/output of data relating to a computation of a plurality of processors in response to an access request from a second input/output unit and an access request from a first input/output unit which requires higher reliability than said second input/output unit, and orders at least one of a plurality of processors to perform a computation relating to the access request from said first input/output unit away from the computation relating to the access request from said second input/output unit in case of that said first input/output unit issued an access request, so that a same computation is made by said plurality of processors; a unit that compares the results of said computations relative to the access request from said first input/output unit provided from said plurality of processors; and a unit that allows the data associated with said computations of said processors to be output on the basis of said compared results.
    Type: Application
    Filed: May 11, 2011
    Publication date: September 1, 2011
    Inventors: Akira Bando, Shin Kokura, Takashi Umehara, Masamitsu Kobayashi, Hisao Nagayama, Naoya Mashiko, Masakazu Ishikawa, Masahiro Shiraishi, Akihiro Onozuka, Hiromichi Endoh, Tsutomu Yamada, Satoru Funaki
  • Publication number: 20110022936
    Abstract: A receiving device including: a receiver receiving two frames, each including substantially same data attached thereto with a data error detection code, a frame error detection code, and safety flag information indicating a safety function or not, respectively; a first detector connected to the receiver for performing error detection of the frames by use of the frame error detection code, respectively; a second detector connected to the receiver for performing error detection of the data by use of the data error detection code, respectively; and a Direct Memory Access Controller (DMAC) connected to the first and second detectors for outputting one among the data included in the two frames under a condition of the safety function in the two frames when no error is detected in the frame and data error detections.
    Type: Application
    Filed: October 8, 2010
    Publication date: January 27, 2011
    Inventors: Akihiro ONOZUKA, Masakazu Ishikawa, Masamitsu Kobayashi, Takashi Umehara, Shin Kokura, Hiromichi Endoh, Satoru Funaki, Hisao Nagayama, Masahiro Shiraishi, Akira Bando, Eiji Kobayashi, Yasuyuki Furuta, Naoya Mashiko
  • Publication number: 20100050062
    Abstract: The system has, provided in a sending device, a generator generating transmission data including data, a data error detection code generated from the data and a safety flag indicating a degree of reliability, and transmission data; has, provided in a receiving device, a plurality of components of extracting transmission data, a safety flag, and a data error detection code from a received frame, and detecting a data error, a comparator comparing the matching of a plurality of received frames, and a selector selecting one received frame, from the frame error detection result, the safety flag, the data error detection result, and the matching comparison result; and determines the validity of transmitted data by the detection corresponding to the degree of reliability set with the safety flag.
    Type: Application
    Filed: October 29, 2009
    Publication date: February 25, 2010
    Inventors: Akihiro ONOZUKA, Masakazu ISHIKAWA, Masamitsu KOBAYASHI, Takashi UMEHARA, Shin KOKURA, Hiromichi ENDOH, Satoru FUNAKI, Hisao NAGAYAMA, Masahiro SHIRAISHI, Akira BANDO, Eiji KOBAYASHI, Yasuyuki FURUTA, Naoya MASHIKO
  • Patent number: 7555627
    Abstract: Input-output devices are prevented from conducting false output due to faulty operation by providing an input-output control apparatus configured to store input-output values to be used by a processor to conduct arithmetic operation in a mode having a relatively high safety requirement, in a first storage area, store input-output values to be used by the processor to conduct arithmetic operation in a mode having a relatively low safety requirement, in a second storage area, and restrict copying to the first storage area, copying from the first storage area, copying to the second storage area, or copying from the second storage area according to the mode concerning the safety requirement.
    Type: Grant
    Filed: June 30, 2006
    Date of Patent: June 30, 2009
    Assignees: Hitachi, Ltd., Hitachi Information & Control Solutions, Ltd.
    Inventors: Naoya Mashiko, Takashi Umehara, Masamitsu Kobayashi, Hiromichi Endoh, Akihiro Onozuka, Akira Bando, Shin Kokura, Hisao Nagayama, Masakazu Ishikawa, Satoru Funaki, Masahiro Shiraishi
  • Publication number: 20070239916
    Abstract: Input-output devices are prevented from conducting false output due to faulty operation by providing an input-output control apparatus configured to store input-output values to be used by a processor to conduct arithmetic operation in a mode having a relatively high safety requirement, in a first storage area, store input-output values to be used by the processor to conduct arithmetic operation in a mode having a relatively low safety requirement, in a second storage area, and restrict copying to the first storage area, copying from the first storage area, copying to the second storage area, or copying from the second storage area according to the mode concerning the safety requirement.
    Type: Application
    Filed: June 30, 2006
    Publication date: October 11, 2007
    Inventors: Naoya Mashiko, Takashi Umehara, Masamitsu Kobayashi, Hiromichi Endoh, Akihiro Onozuka, Akira Bando, Shin Kokura, Hisao Nagayama, Masakazu Ishikawa, Satoru Funaki, Masahiro Shiraishi
  • Publication number: 20070006025
    Abstract: The system has, provided in a sending device, a generator generating transmission data including data, a data error detection code generated from the data and a safety flag indicating a degree of reliability, and transmission data; has, provided in a receiving device, a plurality of components of extracting transmission data, a safety flag, and a data error detection code from a received frame, and detecting a data error, a comparator comparing the matching of a plurality of received frames, and a selector selecting one received frame, from the frame error detection result, the safety flag, the data error detection result, and the matching comparison result; and determines the validity of transmitted data by the detection corresponding to the degree of reliability set with the safety flag.
    Type: Application
    Filed: June 30, 2006
    Publication date: January 4, 2007
    Inventors: Akihiro Onozuka, Masakazu Ishikawa, Masamitsu Kobayashi, Takashi Umehara, Shin Kokura, Hiromichi Endoh, Satoru Funaki, Hisao Nagayama, Masahiro Shiraishi, Akira Bando, Eiji Kobayashi, Yasuyuki Furuta, Naoya Mashiko
  • Publication number: 20060282702
    Abstract: Processed results are received when processors make compatible computations on data of a common object. A computation command signal is generated and fed to the processors in response to a start signal from any one of the processors so that the processors can make computations with different operation timings. Then, the results of the computations made by the processors are compared with each other. Thus, apparatus capable of small size, high performance and safety at the same time can be achieved by the above construction using the processors.
    Type: Application
    Filed: June 7, 2006
    Publication date: December 14, 2006
    Inventors: Akira Bando, Shin Kokura, Takashi Umehara, Masamitsu Kobayashi, Hisao Nagayama, Naoya Mashiko, Masahiro Shiraishi, Masakazu Ishikawa, Akihiro Onozuka, Hiromichi Endoh, Tsutomu Yamada, Satoru Funaki