Abstract: A cell count determination device is configured to determine a cell count of a battery pack having installed therein a plurality of battery cells. The cell count determination device includes a plurality of switch elements provided in association with the plurality of battery cells, which can be increased or decreased in number in the battery pack. Each of the switch elements is configured to enter a conductive state if, while connected to the battery pack, a corresponding battery cell is present, and enter a non-conductive state if the corresponding battery cell is not present. The cell count determination device further includes a determination unit that is configured to determine the cell count of the connected battery pack on the basis of a combination of conductive states and non-conductive states among the plurality of switch elements.

Abstract: A cell count determination device is configured to determine a cell count of a battery pack having installed therein a plurality of battery cells. The cell count determination device includes a plurality of switch elements provided in association with the plurality of battery cells, which can be increased or decreased in number in the battery pack. Each of the switch elements is configured to enter a conductive state if, while connected to the battery pack, a corresponding battery cell is present, and enter a non-conductive state if the corresponding battery cell is not present. The cell count determination device further includes a determination unit that is configured to determine the cell count of the connected battery pack on the basis of a combination of conductive states and non-conductive states among the plurality of switch elements.

Abstract: An electrostatic protection element includes a substrate of a first conductivity type, an epitaxial layer formed on the substrate, the epitaxial layer being of a second conductivity type; a well formed on the epitaxial layer, the well being of the first conductivity type; a transistor formed inside of the well, the transistor including a drain region, a source region formed to face the drain region across a channel region, and a gate formed above the channel region so as to be insulated; and a well contact region of the first conductivity type disposed so as to form an opposing region where the drain region and the well contact region face each other while being separated by a prescribed distance in a direction parallel to at least an extension direction of the gate.

Abstract: A semiconductor device including plural first switches, each provided so as to correspond to one of plural battery cells connected in series, each first switch including one end connected to a corresponding battery cell and another end connected to one electrode of a corresponding charge storage section of plural charge storage sections, each of the charge storage sections being provided so as to correspond to one of the plural battery cells, and another electrode of each charge storage section being connected to a fixed potential; plural second switches, each provided so as to correspond to one of the plural first switches, each second switch including one end connected to the other end of the corresponding first switch; and processing section connected to each other end of the plural second switches, that processes voltages supplied via the second switches.

Abstract: An electrostatic protection element includes a substrate of a first conductivity type, an epitaxial layer formed on the substrate, the epitaxial layer being of a second conductivity type; a well formed on the epitaxial layer, the well being of the first conductivity type; a transistor formed inside of the well, the transistor including a drain region, a source region formed to face the drain region across a channel region, and a gate formed above the channel region so as to be insulated; and a well contact region of the first conductivity type disposed so as to form an opposing region where the drain region and the well contact region face each other while being separated by a prescribed distance in a direction parallel to at least an extension direction of the gate.

Abstract: The battery monitoring chips each include a battery monitoring function section that is provided so as to correspond to a respective battery cell group and to monitor a state of each battery cell contained in the corresponding battery cell group, and a regulator that generates a drive voltage to supply to a configuration circuit of the battery monitoring function section based on power supplied from the battery. The battery monitoring chips are connected together in series to give a communication path, with an input end of the regulator electrically connected to an output end of another regulator. A microcomputer is connected to a battery monitoring chip, and is driven by a drive voltage generated by the regulator of the battery monitoring chip accompanying power consumption by each of the battery cells.

Abstract: A resistance structure including: a conductive layer provided at a surface layer portion of a semiconductor substrate; a first resistance element having long sides and short sides provided over the conductive layer with an insulating film interposed; a second resistance element having long sides and short sides provided over the conductive layer with the insulating film interposed and disposed such that one long side thereof opposes one long side of the first resistance element; first wiring that is connected to one end of the first resistance element; second wiring that is connected to one end of the second resistance element; third wiring that connects the other end of the first resistance element with the other end of the second resistance element; and a connection portion that connects any of the first wiring, the second wiring and the third wiring with the conductive layer.

Abstract: The present disclosure provides a semiconductor device including: plural first switches, each provided so as to correspond to one of plural battery cells connected in series, each first switch including one end connected to a corresponding battery cell and another end connected to one electrode of a corresponding charge storage section of plural charge storage sections, each of the charge storage sections being provided so as to correspond to one of the plural battery cells, and another electrode of each charge storage section being connected to a fixed potential; plural second switches, each provided so as to correspond to one of the plural first switches, each second switch including one end connected to the other end of the corresponding first switch; and processing section connected to each other end of the plural second switches, that processes voltages supplied via the second switches.

Abstract: A resistance structure including: a conductive layer provided at a surface layer portion of a semiconductor substrate; a first resistance element having long sides and short sides provided over the conductive layer with an insulating film interposed; a second resistance element having long sides and short sides provided over the conductive layer with the insulating film interposed and disposed such that one long side thereof opposes one long side of the first resistance element; first wiring that is connected to one end of the first resistance element; second wiring that is connected to one end of the second resistance element; third wiring that connects the other end of the first resistance element with the other end of the second resistance element; and a connection portion that connects any of the first wiring, the second wiring and the third wiring with the conductive layer.

Abstract: The battery monitoring chips each include a battery monitoring function section that is provided so as to correspond to a respective battery cell group and to monitor a state of each battery cell contained in the corresponding battery cell group, and a regulator that generates a drive voltage to supply to a configuration circuit of the battery monitoring function section based on power supplied from the battery. The battery monitoring chips are connected together in series to give a communication path, with an input end of the regulator electrically connected to an output end of another regulator. A microcomputer is connected to a battery monitoring chip, and is driven by a drive voltage generated by the regulator of the battery monitoring chip accompanying power consumption by each of the battery cells.

Abstract: A resistance structure including: a conductive layer provided at a surface layer portion of a semiconductor substrate; a first resistance element having long sides and short sides provided over the conductive layer with an insulating film interposed; a second resistance element having long sides and short sides provided over the conductive layer with the insulating film interposed and disposed such that one long side thereof opposes one long side of the first resistance element; first wiring that is connected to one end of the first resistance element; second wiring that is connected to one end of the second resistance element; third wiring that connects the other end of the first resistance element with the other end of the second resistance element; and a connection portion that connects any of the first wiring, the second wiring and the third wiring with the conductive layer.

Abstract: A semiconductor device includes first and second wells formed side by side as impurity diffusion regions of a first conductive type in a semiconductor substrate, below an intermediate dielectric film that covers a major surface of the substrate. A conductive layer formed above the intermediate dielectric film is held at a potential. A first resistive layer is formed on the intermediate dielectric film and is electrically connected to the first well. A second resistive layer is formed on the intermediate dielectric film and is electrically connected to the second well. The first resistive layer and first well form a first resistance element. The second resistive layer and second well form a second resistance element.

Abstract: A resistance structure including: a conductive layer provided at a surface layer portion of a semiconductor substrate; a first resistance element having long sides and short sides provided over the conductive layer with an insulating film interposed; a second resistance element having long sides and short sides provided over the conductive layer with the insulating film interposed and disposed such that one long side thereof opposes one long side of the first resistance element; first wiring that is connected to one end of the first resistance element; second wiring that is connected to one end of the second resistance element; third wiring that connects the other end of the first resistance element with the other end of the second resistance element; and a connection portion that connects any of the first wiring, the second wiring and the third wiring with the conductive layer.

Abstract: A semiconductor device includes first and second wells formed side by side as impurity diffusion regions of a first conductive type in a semiconductor substrate, below an intermediate dielectric film that covers a major surface of the substrate. A conductive layer formed above the intermediate dielectric film is held at a potential. A first resistive layer is formed on the intermediate dielectric film and is electrically connected to the first well. A second resistive layer is formed on the intermediate dielectric film and is electrically connected to the second well. The first resistive layer and first well form a first resistance element. The second resistive layer and second well form a second resistance element.

Abstract: In a replica circuit, a potential simulating a waveform of current passing through an inductor is generated as a referential potential. A timing when the referential potential and an output potential become substantially the same as each other and a timing when the current passing through the inductor becomes substantially zero are set to substantially correspond to each other. A control circuit turns off an NMOS transistor at a time when the current passing through the inductor becomes lower than 0 [A]. At this time, a PMOS transistor is already turned off. Therefore, the current passing through the inductor can be reliably prevented from flowing in reverse to the switch element.

Abstract: A circuit includes a reset circuit body and a delay circuit. The circuit body outputs a signal which indicates a reset when the supply of a supply voltage is initiated until the supply voltage reaches a sufficient value and indicates release of the reset after it reaches the sufficient value. The delay circuit outputs a signal obtained by delaying start of the indication of the release of the reset, taking into consideration of a sharp rise of the supply voltage. The reset circuit may include a circuit for eliminating a momentary change indicating the reset, and a selection circuit for selecting either an output of the delay circuit or an output of the momentary reset indication elimination circuit.

Abstract: In a replica circuit, a potential simulating a waveform of current passing through an inductor is generated as a referential potential. A timing when the referential potential and an output potential become substantially the same as each other and a timing when the current passing through the inductor becomes substantially zero are set to substantially correspond to each other. A control circuit turns off an NMOS transistor at a time when the current passing through the inductor becomes lower than 0 [A]. At this time, a PMOS transistor is already turned off Therefore, the current passing through the inductor can be reliably prevented from flowing in reverse to the switch element.

Abstract: A circuit includes a reset circuit body and a delay circuit. The circuit body outputs a signal which indicates a reset when the supply of a supply voltage is initiated until the supply voltage reaches a sufficient value and indicates release of the reset after it reaches the sufficient value. The delay circuit outputs a signal obtained by delaying start of the indication of the release of the reset, taking into consideration of a sharp rise of the supply voltage. The reset circuit may include a circuit for eliminating a momentary change indicating the reset, and a selection circuit for selecting either an output of the delay circuit or an output of the momentary reset indication elimination circuit.

Abstract: The present invention relates to an ATP-regeneration reaction system comprising the steps of acting adenylate kinase on AMP to convert it into ADP and acting a polyphosphoric acid synthetase in the presence of a polyphosphoric acid compound to convert it into ATP and a polyphosphoric acid compound; an ATP-regeneration reaction system comprising the steps of acting a phosphotransferase on AMP in the presence of a polyphosphoric acid compound to convert it into ADP and then acting a polyphosphoric acid synthetase on the resulting ADP to convert it into ATP; and a method for detecting or inspecting adenine nucleotide or RNA and an ATP-amplification method, which make use of the foregoing regeneration system.

Abstract: There are provided a plasmid characterized by having the nucleotide sequence of SEQ ID NO: 1, a plasmid characterized by having the nucleotide sequence of SEQ ID NO: 2, a plasmid characterized by having at least a part of the nucleotide sequences of SEQ ID NOs: 1 and 2 and further containing a selective marker gene, each plasmid being usable as a transformation vector for effecting gene manipulation in ammonia oxidizing bacteria, and transformants characterized in that they are obtained by transferring these plasmids into host organisms.