Abstract: An apparatus for analyzing faults in a memory having a redundancy circuit, includes an algorithmic pattern generator which generates address signals to select a memory cell of a memory under test and data which is written to a selected memory cell, a comparison circuit for performing a read operation after data has been written to a selected memory cell by address signals and comparing the data read and the data from the algorithmic pattern generator to determine whether or not it is in agreement and if it is not in agreement generating a fault signal that indicates that the memory cell is faulty, a fault analysis memory having a number of memory cells, and an address allocation circuit which receives address signals from the algorithmic pattern generator and performs address allocation for the fault analysis memory so that a number of memory cells of the memory under test correspond, based on a predetermined rule, to a single memory cell of the fault analysis memory.

Abstract: A testing apparatus for a memory IC with a redundancy circuit includes a first memory, a counter, a second memory and a comparator. The first memory has a memory area for row addresses or column addresses of a target memory with a redundancy circuit, and stores row addresses or column addresses of defective bits of the target memory. The counter counts the number of defective-bit containing rows or columns of the target memory. The second memory stores a number of rows or columns of spare memory cells provided in the redundancy circuit. The comparator compares a count value of the counter with the number stored in the second memory. When the count value of the counter exceeds the number of rows or columns of spare memory cells stored in the second memory, it is considered unrepairable and test is terminated.