Patents by Inventor Hisao Yanagi

Hisao Yanagi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 4799040
    Abstract: A data conversion circuit is constructed in such a manner that a plurality of flip-flop series, each including tandem connected master/slave flip-flops, are provided and driven by plural phase numbers of clock signals which have no overlap therebetween, so that a parallel data is obtained with a serial data supplied to the flip-flop series, or a serial data is obtained with a parallel data supplied to the flip-flop series. The clock signals employed here have no overlap between each of the corresponding phases of the signals.
    Type: Grant
    Filed: January 30, 1987
    Date of Patent: January 17, 1989
    Assignee: Tokyo Shibaura Denki Kabushiki Kaisha
    Inventor: Hisao Yanagi
  • Patent number: 4363107
    Abstract: A binary multiplication cell circuit suitable for a MOS transistor integrated circuit. The cell circuit has a NOR circuit for obtaining a partial product of one binary digit of a multiplicand and one binary digit of a multiplier and a full adder for obtaining result of multiplication (or augend) and a carry digit based on the partial product, an augend supplied from a given multiplication cell circuit and a carry digit supplied from another given multiplication cell circuit. The full adder comprises two AND circuits, three NOR circuits, an inverter and an exclusive OR circuit. Preferably, the exclusive OR circuit is constituted by an exclusive NOR circuit and an inverter.
    Type: Grant
    Filed: September 30, 1980
    Date of Patent: December 7, 1982
    Assignee: Tokyo Shibaura Denki Kabushiki Kaisha
    Inventors: Masahide Ohhashi, Hisao Yanagi