Patents by Inventor Hisao Yoshimura

Hisao Yoshimura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9693703
    Abstract: An electrocardiogram display device includes an electrocardiogram waveform generating unit that generates electrocardiogram waveforms of a plurality of leads based on electrocardiogram data of each of the leads, an arranging instruction unit that instructs an arranging order of the electrocardiogram waveform of each lead by performing inputting, a display unit, and a displaying control unit that arranging the electrocardiogram waveform of each lead in a corresponding arranging order in response to instruction of the arranging instruction unit to create and display one screen image on the display unit.
    Type: Grant
    Filed: September 28, 2015
    Date of Patent: July 4, 2017
    Assignee: NIHON KOHDEN CORPORATION
    Inventor: Hisao Yoshimura
  • Publication number: 20160095526
    Abstract: An electrocardiogram display device includes an electrocardiogram waveform generating unit that generates electrocardiogram waveforms of a plurality of leads based on electrocardiogram data of each of the leads, an arranging instruction unit that instructs an arranging order of the electrocardiogram waveform of each lead by performing inputting, a display unit, and a displaying control unit that arranging the electrocardiogram waveform of each lead in a corresponding arranging order in response to instruction of the arranging instruction unit to create and display one screen image on the display unit.
    Type: Application
    Filed: September 28, 2015
    Publication date: April 7, 2016
    Inventor: Hisao YOSHIMURA
  • Patent number: 7638432
    Abstract: The present invention provides a semiconductor device, comprising a semiconductor substrate, a gate insulating film formed on the semiconductor substrate, a gate electrode formed on the gate insulating film, and source-drain diffusion layer formed within the semiconductor substrate in the vicinity of the gate electrode. A silicide film is formed on each of the gate electrode and the source-drain diffusion layer. The silicide film positioned on the gate electrode is thicker than the silicide film positioned on the source-drain diffusion layer. The present invention also provides a method of manufacturing a semiconductor device, in which a gate electrode is formed on a gate insulating film covering a semiconductor substrate, followed by forming a source-drain diffusion layer within the semiconductor substrate.
    Type: Grant
    Filed: April 23, 2007
    Date of Patent: December 29, 2009
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Katsura Miyashita, Hisao Yoshimura, Mariko Takagi
  • Publication number: 20070194382
    Abstract: The present invention provides a semiconductor device, comprising a semiconductor substrate, a gate insulating film formed on the semiconductor substrate, a gate electrode formed on the gate insulating film, and source-drain diffusion layer formed within the semiconductor substrate in the vicinity of the gate electrode. A silicide film is formed on each of the gate electrode and the source-drain diffusion layer. The silicide film positioned on the gate electrode is thicker than the silicide film positioned on the source-drain diffusion layer. The present invention also provides a method of manufacturing a semiconductor device, in which a gate electrode is formed on a gate insulating film covering a semiconductor substrate, followed by forming a source-drain diffusion layer within the semiconductor substrate.
    Type: Application
    Filed: April 23, 2007
    Publication date: August 23, 2007
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Katsura Miyashita, Hisao Yoshimura, Mariko Takagi
  • Patent number: 7220672
    Abstract: The invention provides a semiconductor device, and a manufacturing method, comprising a semiconductor substrate, a gate insulating film, a gate electrode, and a source-drain diffusion layer. A silicide film is formed on the gate electrode and the source-drain diffusion layer. The silicide film is thicker on the gate electrode than on the source-drain diffusion layer. The manufacturing method comprises forming a gate electrode on a gate insulating film, followed by forming a source-drain diffusion layer. Then, atoms inhibiting a silicidation are selectively introduced into the source-drain diffusion layer, and a high melting point metal film is formed on the gate electrode and the source-drain diffusion layer. The high melting point metal film is converted into silicide films selectively on the gate electrode and the source-drain diffusion layer.
    Type: Grant
    Filed: February 8, 2005
    Date of Patent: May 22, 2007
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Katsura Miyashita, Hisao Yoshimura, Mariko Takagi
  • Publication number: 20050158958
    Abstract: The present invention provides a semiconductor device, comprising a semiconductor substrate, a gate insulating film formed on the semiconductor substrate, a gate electrode formed on the gate insulating film, and source-drain diffusion layer formed within the semiconductor substrate in the vicinity of the gate electrode. A silicide film is formed on each of the gate electrode and the source-drain diffusion layer. The silicide film positioned on the gate electrode is thicker than the silicide film positioned on the source-drain diffusion layer. The present invention also provides a method of manufacturing a semiconductor device, in which a gate electrode is formed on a gate insulating film covering a semiconductor substrate, followed by forming a source-drain diffusion layer within the semiconductor substrate.
    Type: Application
    Filed: February 8, 2005
    Publication date: July 21, 2005
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Katsura Miyashita, Hisao Yoshimura, Mariko Takagi
  • Patent number: 6869867
    Abstract: The present invention provides a semiconductor device, comprising a semiconductor substrate, a gate insulating film formed on the semiconductor substrate, a gate electrode formed on the gate insulating film, and source-drain diffusion layer formed within the semiconductor substrate in the vicinity of the gate electrode. A silicide film is formed on each of the gate electrode and the source-drain diffusion layer. The silicide film positioned on the gate electrode is thicker than the silicide film positioned on the source-drain diffusion layer. The present invention also provides a method of manufacturing a semiconductor device, in which a gate electrode is formed on a gate insulating film covering a semiconductor substrate, followed by forming a source-drain diffusion layer within the semiconductor substrate.
    Type: Grant
    Filed: July 30, 2001
    Date of Patent: March 22, 2005
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Katsura Miyashita, Hisao Yoshimura, Mariko Takagi
  • Publication number: 20010045605
    Abstract: The present invention provides a semiconductor device, comprising a semiconductor substrate, a gate insulating film formed on the semiconductor substrate, a gate electrode formed on the gate insulating film, and source-drain diffusion layer formed within the semiconductor substrate in the vicinity of the gate electrode. A silicide film is formed on each of the gate electrode and the source-drain diffusion layer. The silicide film positioned on the gate electrode is thicker than the silicide film positioned on the source-drain diffusion layer. The present invention also provides a method of manufacturing a semiconductor device, in which a gate electrode is formed on a gate insulating film covering a semiconductor substrate, followed by forming a source-drain diffusion layer within the semiconductor substrate.
    Type: Application
    Filed: July 30, 2001
    Publication date: November 29, 2001
    Inventors: Katsura Miyashita, Hisao Yoshimura, Mariko Takagi
  • Patent number: 6037605
    Abstract: A semiconductor device includes spaced apart source and drain regions formed in a semiconductor substrate and a gate electrode insulatively spaced from a channel region between the source region and the drain region by a gate insulating film. Insulating layers are respectively formed between the source region and the channel region and between the drain region and the channel region.
    Type: Grant
    Filed: August 19, 1997
    Date of Patent: March 14, 2000
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Hisao Yoshimura
  • Patent number: 5677229
    Abstract: A method for manufacturing a semiconductor device of the present invention has the step of forming an insulation material on a main surface of a semiconductor substrate. A groove is formed to extend from the surface of the material film to the substrate. The groove is buried with a first insulation film. By use of the first insulation film as an etching mask, the material film is removed, so that a projecting portion projecting to the first insulation film from the main surface can be obtained. A second insulation film is formed on a side surface of the projecting portion in a sloped shape, which is from the top portion of the projecting portion to the main surface.
    Type: Grant
    Filed: April 28, 1995
    Date of Patent: October 14, 1997
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shigeru Morita, Fumitomo Matsuoka, Hisao Yoshimura, Takeo Maeda
  • Patent number: 5506168
    Abstract: A method for manufacturing a semiconductor device of the present invention has the step of forming an insulation material on a main surface of a semiconductor substrate. A groove is formed to extend from the surface of the material film to the substrate. The groove is buried with a first insulation film. By use of the first insulation film as an etching mask, the material film is removed, so that a projecting portion projecting to the first insulation film from the main surface can be obtained. A second insulation film is formed on a side surface or the projecting portion in a slope shape, which is from the top portion of the projecting portion to the main surface.
    Type: Grant
    Filed: October 11, 1994
    Date of Patent: April 9, 1996
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shigeru Morita, Fumitomo Matsuoka, Hisao Yoshimura, Takeo Maeda
  • Patent number: 5489795
    Abstract: A semiconductor device has a first P type well region (11) formed on an N type semiconductor substrate (10) and a second N type well region (12) formed so as to enclose the first well region. A third N type well region (13) formed on the semiconductor substrate is enclosed by a fourth P type well region (14). The first well region adjoins and is electrically connected to the fourth well region. Contact regions (15, 16) are formed on the first and third well regions to apply a bias voltage to the PN junction between the first and third well regions. An NMOS FET is formed in the first well region and a PMOS FET is formed in the third well region. The drain currents of the NMOS FET and PMOS FET are controlled by changing the reverse bias voltage applied to the two contact regions (15, 16). The depth of the first well region (11) is such that a depletion layer extending below the NMOS FET gate electrode (50) can be connected to a depletion layer formed at an interface between the first and second well regions.
    Type: Grant
    Filed: October 4, 1994
    Date of Patent: February 6, 1996
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hisao Yoshimura, Takeo Maeda, Masakazu Kakumu