Patents by Inventor Hisao Yoshimura
Hisao Yoshimura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11523070Abstract: Color mixing between pixels is prevented in a solid-state imaging element in which a pair of pixels for detecting the phase difference of a pair of light rays are arranged. A pair of photoelectric conversion elements receive a pair of light rays made by pupil-splitting. A floating diffusion layer generates a pair of pixel signals from electric charge transferred from each of the pair of photoelectric conversion elements. A pair of transfer transistors transfer the electric charge from the pair of photoelectric conversion elements to the floating diffusion layer. In a case of detecting the phase difference of the pair of light rays from the pair of pixel signals, the control unit takes control so that back gate voltages that include the back gate potentials of both of the pair of transfer transistors with respect to the potential barrier between the pair of photoelectric conversion elements have values different from values in a case of synthesizing the pair of pixel signals.Type: GrantFiled: May 17, 2019Date of Patent: December 6, 2022Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATIONInventors: Hisao Yoshimura, Ryoji Suzuki
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Publication number: 20220359584Abstract: A photodetector including a plurality of photoelectric conversion sections that is provided to a semiconductor substrate. The photoelectric conversion sections each include a first region of a first electrical conduction type that is provided on a first surface side of the semiconductor substrate, a second region of a second electrical conduction type that is provided on a second surface side of the semiconductor substrate opposite to the first surface, a third region of a third electrical conduction type that is provided in a region between the first region and the second region of the semiconductor substrate, a first electrode that is electrically coupled to the first region from the first surface side, and a second electrode that is electrically coupled to the second region from the second surface side. The third region absorbs incident light.Type: ApplicationFiled: March 30, 2020Publication date: November 10, 2022Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATIONInventors: Takahiro HAMASAKI, Koji NAGAHIRO, Hiroyuki OHRI, Satoe MIYATA, Takahiro MIURA, Hisao YOSHIMURA
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Publication number: 20220278141Abstract: A photodetector according to an embodiment of the present disclosure including a plurality of photoelectric conversion sections that is provided to a semiconductor substrate. The photoelectric conversion sections each include a first region of a first electrical conduction type that is provided on a first surface side of the semiconductor substrate, a second region of a second electrical conduction type that is provided on a second surface side of the semiconductor substrate opposite to the first surface, a third region of a third electrical conduction type that is provided in a region between the first region and the second region of the semiconductor substrate, a first electrode that extends from the second surface in a thickness direction of the semiconductor substrate, a pixel separation layer having an insulation property, and a second electrode that is electrically coupled to the second region from the second surface side. The third region absorbs incident light.Type: ApplicationFiled: March 30, 2020Publication date: September 1, 2022Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATIONInventors: Takahiro HAMASAKI, Hiroyuki TAKASHINO, Koji NAGAHIRO, Hiroyuki OHRI, Satoe MIYATA, Takahiro MIURA, Hisao YOSHIMURA
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Publication number: 20210352228Abstract: Color mixing between pixels is prevented in a solid-state imaging element in which a pair of pixels for detecting the phase difference of a pair of light rays are arranged. A pair of photoelectric conversion elements receive a pair of light rays made by pupil-splitting. A floating diffusion layer generates a pair of pixel signals from electric charge transferred from each of the pair of photoelectric conversion elements. A pair of transfer transistors transfer the electric charge from the pair of photoelectric conversion elements to the floating diffusion layer. In a case of detecting the phase difference of the pair of light rays from the pair of pixel signals, the control unit takes control so that back gate voltages that include the back gate potentials of both of the pair of transfer transistors with respect to the potential barrier between the pair of photoelectric conversion elements have values different from values in a case of synthesizing the pair of pixel signals.Type: ApplicationFiled: May 17, 2019Publication date: November 11, 2021Inventors: HISAO YOSHIMURA, RYOJI SUZUKI
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Patent number: 9693703Abstract: An electrocardiogram display device includes an electrocardiogram waveform generating unit that generates electrocardiogram waveforms of a plurality of leads based on electrocardiogram data of each of the leads, an arranging instruction unit that instructs an arranging order of the electrocardiogram waveform of each lead by performing inputting, a display unit, and a displaying control unit that arranging the electrocardiogram waveform of each lead in a corresponding arranging order in response to instruction of the arranging instruction unit to create and display one screen image on the display unit.Type: GrantFiled: September 28, 2015Date of Patent: July 4, 2017Assignee: NIHON KOHDEN CORPORATIONInventor: Hisao Yoshimura
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Publication number: 20160095526Abstract: An electrocardiogram display device includes an electrocardiogram waveform generating unit that generates electrocardiogram waveforms of a plurality of leads based on electrocardiogram data of each of the leads, an arranging instruction unit that instructs an arranging order of the electrocardiogram waveform of each lead by performing inputting, a display unit, and a displaying control unit that arranging the electrocardiogram waveform of each lead in a corresponding arranging order in response to instruction of the arranging instruction unit to create and display one screen image on the display unit.Type: ApplicationFiled: September 28, 2015Publication date: April 7, 2016Inventor: Hisao YOSHIMURA
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Patent number: 7638432Abstract: The present invention provides a semiconductor device, comprising a semiconductor substrate, a gate insulating film formed on the semiconductor substrate, a gate electrode formed on the gate insulating film, and source-drain diffusion layer formed within the semiconductor substrate in the vicinity of the gate electrode. A silicide film is formed on each of the gate electrode and the source-drain diffusion layer. The silicide film positioned on the gate electrode is thicker than the silicide film positioned on the source-drain diffusion layer. The present invention also provides a method of manufacturing a semiconductor device, in which a gate electrode is formed on a gate insulating film covering a semiconductor substrate, followed by forming a source-drain diffusion layer within the semiconductor substrate.Type: GrantFiled: April 23, 2007Date of Patent: December 29, 2009Assignee: Kabushiki Kaisha ToshibaInventors: Katsura Miyashita, Hisao Yoshimura, Mariko Takagi
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Publication number: 20070194382Abstract: The present invention provides a semiconductor device, comprising a semiconductor substrate, a gate insulating film formed on the semiconductor substrate, a gate electrode formed on the gate insulating film, and source-drain diffusion layer formed within the semiconductor substrate in the vicinity of the gate electrode. A silicide film is formed on each of the gate electrode and the source-drain diffusion layer. The silicide film positioned on the gate electrode is thicker than the silicide film positioned on the source-drain diffusion layer. The present invention also provides a method of manufacturing a semiconductor device, in which a gate electrode is formed on a gate insulating film covering a semiconductor substrate, followed by forming a source-drain diffusion layer within the semiconductor substrate.Type: ApplicationFiled: April 23, 2007Publication date: August 23, 2007Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Katsura Miyashita, Hisao Yoshimura, Mariko Takagi
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Patent number: 7220672Abstract: The invention provides a semiconductor device, and a manufacturing method, comprising a semiconductor substrate, a gate insulating film, a gate electrode, and a source-drain diffusion layer. A silicide film is formed on the gate electrode and the source-drain diffusion layer. The silicide film is thicker on the gate electrode than on the source-drain diffusion layer. The manufacturing method comprises forming a gate electrode on a gate insulating film, followed by forming a source-drain diffusion layer. Then, atoms inhibiting a silicidation are selectively introduced into the source-drain diffusion layer, and a high melting point metal film is formed on the gate electrode and the source-drain diffusion layer. The high melting point metal film is converted into silicide films selectively on the gate electrode and the source-drain diffusion layer.Type: GrantFiled: February 8, 2005Date of Patent: May 22, 2007Assignee: Kabushiki Kaisha ToshibaInventors: Katsura Miyashita, Hisao Yoshimura, Mariko Takagi
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Publication number: 20050158958Abstract: The present invention provides a semiconductor device, comprising a semiconductor substrate, a gate insulating film formed on the semiconductor substrate, a gate electrode formed on the gate insulating film, and source-drain diffusion layer formed within the semiconductor substrate in the vicinity of the gate electrode. A silicide film is formed on each of the gate electrode and the source-drain diffusion layer. The silicide film positioned on the gate electrode is thicker than the silicide film positioned on the source-drain diffusion layer. The present invention also provides a method of manufacturing a semiconductor device, in which a gate electrode is formed on a gate insulating film covering a semiconductor substrate, followed by forming a source-drain diffusion layer within the semiconductor substrate.Type: ApplicationFiled: February 8, 2005Publication date: July 21, 2005Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Katsura Miyashita, Hisao Yoshimura, Mariko Takagi
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Patent number: 6869867Abstract: The present invention provides a semiconductor device, comprising a semiconductor substrate, a gate insulating film formed on the semiconductor substrate, a gate electrode formed on the gate insulating film, and source-drain diffusion layer formed within the semiconductor substrate in the vicinity of the gate electrode. A silicide film is formed on each of the gate electrode and the source-drain diffusion layer. The silicide film positioned on the gate electrode is thicker than the silicide film positioned on the source-drain diffusion layer. The present invention also provides a method of manufacturing a semiconductor device, in which a gate electrode is formed on a gate insulating film covering a semiconductor substrate, followed by forming a source-drain diffusion layer within the semiconductor substrate.Type: GrantFiled: July 30, 2001Date of Patent: March 22, 2005Assignee: Kabushiki Kaisha ToshibaInventors: Katsura Miyashita, Hisao Yoshimura, Mariko Takagi
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Publication number: 20010045605Abstract: The present invention provides a semiconductor device, comprising a semiconductor substrate, a gate insulating film formed on the semiconductor substrate, a gate electrode formed on the gate insulating film, and source-drain diffusion layer formed within the semiconductor substrate in the vicinity of the gate electrode. A silicide film is formed on each of the gate electrode and the source-drain diffusion layer. The silicide film positioned on the gate electrode is thicker than the silicide film positioned on the source-drain diffusion layer. The present invention also provides a method of manufacturing a semiconductor device, in which a gate electrode is formed on a gate insulating film covering a semiconductor substrate, followed by forming a source-drain diffusion layer within the semiconductor substrate.Type: ApplicationFiled: July 30, 2001Publication date: November 29, 2001Inventors: Katsura Miyashita, Hisao Yoshimura, Mariko Takagi
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Patent number: 6037605Abstract: A semiconductor device includes spaced apart source and drain regions formed in a semiconductor substrate and a gate electrode insulatively spaced from a channel region between the source region and the drain region by a gate insulating film. Insulating layers are respectively formed between the source region and the channel region and between the drain region and the channel region.Type: GrantFiled: August 19, 1997Date of Patent: March 14, 2000Assignee: Kabushiki Kaisha ToshibaInventor: Hisao Yoshimura
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Patent number: 5677229Abstract: A method for manufacturing a semiconductor device of the present invention has the step of forming an insulation material on a main surface of a semiconductor substrate. A groove is formed to extend from the surface of the material film to the substrate. The groove is buried with a first insulation film. By use of the first insulation film as an etching mask, the material film is removed, so that a projecting portion projecting to the first insulation film from the main surface can be obtained. A second insulation film is formed on a side surface of the projecting portion in a sloped shape, which is from the top portion of the projecting portion to the main surface.Type: GrantFiled: April 28, 1995Date of Patent: October 14, 1997Assignee: Kabushiki Kaisha ToshibaInventors: Shigeru Morita, Fumitomo Matsuoka, Hisao Yoshimura, Takeo Maeda
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Patent number: 5506168Abstract: A method for manufacturing a semiconductor device of the present invention has the step of forming an insulation material on a main surface of a semiconductor substrate. A groove is formed to extend from the surface of the material film to the substrate. The groove is buried with a first insulation film. By use of the first insulation film as an etching mask, the material film is removed, so that a projecting portion projecting to the first insulation film from the main surface can be obtained. A second insulation film is formed on a side surface or the projecting portion in a slope shape, which is from the top portion of the projecting portion to the main surface.Type: GrantFiled: October 11, 1994Date of Patent: April 9, 1996Assignee: Kabushiki Kaisha ToshibaInventors: Shigeru Morita, Fumitomo Matsuoka, Hisao Yoshimura, Takeo Maeda
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Patent number: 5489795Abstract: A semiconductor device has a first P type well region (11) formed on an N type semiconductor substrate (10) and a second N type well region (12) formed so as to enclose the first well region. A third N type well region (13) formed on the semiconductor substrate is enclosed by a fourth P type well region (14). The first well region adjoins and is electrically connected to the fourth well region. Contact regions (15, 16) are formed on the first and third well regions to apply a bias voltage to the PN junction between the first and third well regions. An NMOS FET is formed in the first well region and a PMOS FET is formed in the third well region. The drain currents of the NMOS FET and PMOS FET are controlled by changing the reverse bias voltage applied to the two contact regions (15, 16). The depth of the first well region (11) is such that a depletion layer extending below the NMOS FET gate electrode (50) can be connected to a depletion layer formed at an interface between the first and second well regions.Type: GrantFiled: October 4, 1994Date of Patent: February 6, 1996Assignee: Kabushiki Kaisha ToshibaInventors: Hisao Yoshimura, Takeo Maeda, Masakazu Kakumu