Abstract: A semiconductor unit constituting a memory device has a memory chip, a package substrate having three wiring layers. Power-supply surfaces (VDD surface) and (GND surface) are wired on the package substrate while an intra-package DQ bus is wired on an intermediate layer between both of the power-supply surfaces. The memory device has two DQ pins every one intra-package DQ bus. The intra-package DQ bus is connected to a signal terminal pad of the memory chip through a via hole. In view of the two DW pins, a via hole for connecting the intra-package DQ bus with the signal terminal pad constitutes a branch wire.

Abstract: A signal line of a data bus includes first wires on a first board and a second wire on a second board. The second board is installed on the first board to connect the first and second wires with each other in series to establish the signal line. Semiconductor devices are connected with the second wire. In such data bus system, impedance of the second wire is decided according to additional capacitance of the semiconductor device on the second board in order to harmonize impedance of the first board with impedance of the second board.

Abstract: A semiconductor unit constituting a memory device has a memory chip, a package substrate having three wiring layers. Power-supply surfaces (VDD surface) and (GND surface) are wired on the package substrate while an intra-package DQ bus is wired on an intermediate layer between both of the power-supply surfaces. The memory device has two DQ pins every one intra-package DQ bus. The intra-package DQ bus is connected to a signal terminal pad of the memory chip through a via hole. In view of the two DW pins, a via hole for connecting the intra-package DQ bus with the signal terminal pad constitutes a branch wire.

Abstract: To prevent data quality from being deteriorated by reflection from each of memory modules, a semiconductor memory device has a switching circuit located on a mother board in the vicinity of a branching point of the data bus. The switching circuit is controlled by a memory controller to selectively operate the memory modules without substantial reflection from a selected one of the memory modules. To this end, each of the memory modules and the memory controller is terminated with characteristic impedance of the data bus.

Abstract: A signal line of a data bus includes first wires on a first board and a second wire on a second board. The second board is installed on the first board to connect the first and second wires with each other in series to establish the signal line. Semiconductor devices are connected with the second wire. In such data bus system, impedance of the second wire is decided according to additional capacitance of the semiconductor device on the second board in order to harmonize impedance of the first board with impedance of the second board.

Abstract: A synchronous semiconductor memory device has a pseudo internal command signal generator for generating a pseudo internal command signal which controls, in non-synchronizing with an externally inputted clock signal, an internal command signal having been generated in synchronizing with the externally inputted clock signal.

Abstract: A semiconductor memory device has a voltage converter for converting a voltage level of an internal clock signal to obtain a high voltage level clock signal. The high level clock signal accelerates the transmission of the clock signal to latch circuits which control the output transistors of the memory device. Another voltage converter is disposed between the data amplifier and the latch circuit instead of the output of the latch circuit, for prevention of current flowing through both the output transistors.

Abstract: A semiconductor memory device of a synchronous type is disclosed, which has an output control circuit (14) adapted to output signals D2T and D2N by activating one of two conduction control signals D1T or by inactivating both of the conduction control signals in accordance with an output control signal MSK2B or OEB for controlling whether a data output terminal DQ is to be actuated or set into a high impedance, and an output circuit 17 provided with a couple of latch circuits 15 and 16 each adapted to individually latch and output the corresponding conduction control signals in synchronism with an internal synchronizing signal .phi.3. There is further provided an additional latch circuit 13 latching the output control signal in response to an inverted signal of the internal synchronizing signal .phi.3.