Patents by Inventor Hisashi Ariyoshi

Hisashi Ariyoshi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6008509
    Abstract: A heterostructure insulated-gate field effect transistor comprises a channel layer, barrier layer and a contact layer. The barrier layer is made of a material having an electron affinity smaller than that of the channel layer and equal to that of the contact layer. Due to the single heterostructure, the series resistance between the channel layer and the source (drain) electrode can be decreased without employing complicated selective ion implanting or selective epitaxial growing method.
    Type: Grant
    Filed: December 24, 1997
    Date of Patent: December 28, 1999
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Makoto Inai, Hiroyuki Seto, Fujio Okui, Susumu Fukuda, Hisashi Ariyoshi
  • Patent number: 5517162
    Abstract: A dielectric resonator device includes a dielectric member, inner conductors provided in the dielectric member, an outer conductor formed on an outer surface of the dielectric member, signal input and output electrodes formed on the outer surface of the dielectric member opposing a mounting substrate and coupled with the inner conductors, and solder bumps formed on the outer conductor on its surface opposing the mounting substrate and on the signal input and output electrodes. By heating the dielectric resonator device opposing the mounting substrate, electrical and mechanical connections may be made therebetween through the solder bumps, while preventing the formation of solder bridges.
    Type: Grant
    Filed: October 13, 1993
    Date of Patent: May 14, 1996
    Assignee: Murata Manufacturing Co., Ltd.
    Inventor: Hisashi Ariyoshi
  • Patent number: 5306943
    Abstract: A Schottky barrier diode includes a semiconductor substrate, an ohmic electrode formed on a first region of the semiconductor substrate, and a Schottky metal electrode formed on a second region spaced apart from the first region on the semiconductor substrate. The Schottky electrode includes at least one ohmic portion forming an ohmic contact with the semiconductor substrate, whereby rectifying characteristics of the Schottky barrier diode are improved.
    Type: Grant
    Filed: March 30, 1992
    Date of Patent: April 26, 1994
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Hisashi Ariyoshi, Masaaki Sueyoshi, Kouichi Sakamoto, Susumu Fukuda
  • Patent number: 4890370
    Abstract: A manufacturing method for an integrated resonator is disclosed wherein a mass of O.sup.+ ions are implanted into a silicon monocrystal substrate from one side thereof, a buried SiO.sub.2 layer is formed by annealing the ion implanted substrate, an SiO.sub.2 layer is formed on the surface of the substrate by oxidizing it, at least one slit is formed on the SiO.sub.2 layer for etching a predetermined area of the silicon monocrystal layer sandwich between two SiO.sub.2 layers to form a cavity and, a piezo-electric resonator is formed on an area of the surfacial SiO.sub.2 layer corresponding to the cavity in the substrate.
    Type: Grant
    Filed: October 7, 1988
    Date of Patent: January 2, 1990
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Susumu Fukuda, Hisashi Ariyoshi, Toru Kasanami
  • Patent number: 4845044
    Abstract: A production method for producing a semiconductor device by growing a crystalline compound semiconductor on a monocrystalline silicon substrate is comprised of a step for forming a transition domain varying from a monocrystalline silicon layer to a polycrystalline silicon layer in the silicon substrate by implanting oxygen ions into the silicon substrate and annealing the silicon substrate and a step for depositing a compound semiconductor layer on the silicon substrate.
    Type: Grant
    Filed: July 28, 1988
    Date of Patent: July 4, 1989
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Hisashi Ariyoshi, Toru Kasanami, Susumu Fukuda
  • Patent number: 4241359
    Abstract: A semiconductor manufacturing method and device made therefrom by forming an insulating SiO.sub.2 film on both surfaces of a silicon substrate using an ion implantation process to form a buried SiO.sub.2 layer within the substrate a predetermined depth beneath one of the substrate surfaces, isolating a body of the substrate layer lying above the buried layer, and forming a semiconductive device in the isolated body. The surface layers of SiO.sub.2 serve to mechanically balance the internal strains generated within the substrate during the formation of the buried layer and thereby prevent the creation of mechanical imperfections in the surface portions of the substrate.
    Type: Grant
    Filed: March 2, 1978
    Date of Patent: December 23, 1980
    Assignee: Nippon Telegraph and Telephone Public Corporation
    Inventors: Katsutoshi Izumi, Masanobu Doken, Hisashi Ariyoshi