Abstract: A memory system includes semiconductor memory devices and a control device. Each of the semiconductor memory devices includes a first pad to which a first signal is input, a second pad to which a second signal is input, a third pad to which a third signal is input, a memory cell array, a sense amplifier, and a data register. In a first mode, after the first signal is switched, a command set instructing a data out operation is input via the second pad. In a second mode, after the first signal is switched, the command is input via at least the third pad. The control device executes a first operation assigning different addresses to the respective semiconductor memory devices and a second operation causing the modes of the respective semiconductor memory devices to be switched from the first to the second mode.

Abstract: According to one embodiment, a memory system includes an array of memory cells that store two or more bits of data each, and a memory controller to control writing data into the memory cells and reading from the memory cells. When a first command is received from a host, the memory controller reads data designated by the first command from the array and then rewrites the read data back into the array using a writing method in which a lower number of bits per memory cell is written than the originally stored manner of the read data. When a read command designating the rewritten data is received from the host, the memory controller reads from the array and transfers it to the host.

Abstract: According to one embodiment, a memory system includes an array of memory cells that store two or more bits of data each, and a memory controller to control writing data into the memory cells and reading from the memory cells. When a first command is received from a host, the memory controller reads data designated by the first command from the array and then rewrites the read data back into the array using a writing method in which a lower number of bits per memory cell is written than the originally stored manner of the read data. When a read command designating the rewritten data is received from the host, the memory controller reads from the array and transfers it to the host.

Abstract: A memory system includes a memory controller and a semiconductor storage device including a power supply pad, first, second, third, and fourth signal pads to which first, second, third, and fourth signals are respectively input, a memory cell array, a data register, and a control circuit executing an operation to output data stored in the data register through the fourth signal pad. The memory controller performs a mode setting operation by toggling the third signal input, after at least the first or second signal has been switched at a first timing after supplying power to the power supply pad, perform an initial setting operation by transmitting a power-on read command at a second timing after the first timing, and transmit a data-out command, at a third timing after the second timing. The semiconductor storage device receives the power-on read and data-out commands via the first and second signal pads.

Abstract: According to one embodiment, a memory system includes an array of memory cells that store two or more bits of data each, and a memory controller to control writing data into the memory cells and reading from the memory cells. When a first command is received from a host, the memory controller reads data designated by the first command from the array and then rewrites the read data back into the array using a writing method in which a lower number of bits per memory cell is written than the originally stored manner of the read data. When a read command designating the rewritten data is received from the host, the memory controller reads from the array and transfers it to the host.

Abstract: A memory system includes semiconductor memory devices and a control device. Each of the semiconductor memory devices includes a first pad to which a first signal is input, a second pad to which a second signal is input, a third pad to which a third signal is input, a memory cell array, a sense amplifier, and a data register. In a first mode, after the first signal is switched, a command set instructing a data out operation is input via the second pad. In a second mode, after the first signal is switched, the command is input via at least the third pad. The control device executes a first operation assigning different addresses to the respective semiconductor memory devices and a second operation causing the modes of the respective semiconductor memory devices to be switched from the first to the second mode.

Abstract: An information processing system includes a host and a memory system. A processor of the host is configured to: determine a logical address of read data and a size of the read data; prepare third information related to the read data other than the logical address of the read data and the size of the read data, the third information being information necessary for the memory system to transmit the read data to the host; and transmit, to the memory system, a command requesting to transmit the read data. A memory controller of the memory system is configured to, in response to receiving the command from the host, transmit a request for the third information to the host. The processor of the host is further configured to, in response to receiving the request from the memory system, transmit the third information to the memory system.

Abstract: A support structure for packaging is provided for containing, storing and transporting electronic components like liquid crystal modules. The structure includes a bottom plate and first and second side plates provided at respective sides of the bottom plate. Side surfaces of the bottom plate constitute first inclined planes slanted at a first degree. End surfaces of the first and second side plates on the bottom plate side constitute second inclined planes slanted at a second degree. The first and second degrees are selected such that, when the first and second side plates are erected to cause the first and second inclined planes to closely contact with each other, the first and second side plates are prevented from being bent inwards more than 90 degrees.

Abstract: A sealed bag for vacuum-packing an electronic device in the state of being evacuated and partially thermally fused at an opening thereof includes a multi-layer film including; a first anti-static layer; a thin metal layer; an insulative layer; and a second anti-static layer. A container includes a case for accommodating at least two such sealed bags. The case is provided with a charge protective layer on an inner surface thereof; a housing for accommodating at least two cases; and a master carton for accommodating at least one housing.

Abstract: As to a packing container, when a corrugated cardboard sheet where metallic foil is stuck on one of its sides is assembled so as to have a box-shape, an edge left for applying paste and a side on which the edge left for applying paste is stuck are connected by metallic foil tape so that metallic foil on the sides inside the box joins along an internal circumferential surface of the box. As a result, since a closed path is formed along the internal circumference of the packing container, partial charging of a packing container is prevented by short-circuiting or shielding charged static electricity, and an electrostatic breakdown of contents, such as a semiconductor device, is prevented.

Abstract: A sealed bag for vacuum-packing an electronic device in the state of being evacuated and partially thermally fused at an opening thereof includes a multi-layer film including; a first anti-static layer; a thin metal layer; an insulative layer; and a second anti-static layer. A container includes a case for accommodating at least two such sealed bags. The case is provided with a charge protective layer on an inner surface thereof; a housing for accommodating at least two cases; and a master carton for accommodating at least one housing.