Patents by Inventor Hisashi Hasegawa

Hisashi Hasegawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11955149
    Abstract: In general, according to one embodiment, a disk device includes a magnetic disk, a magnetic head, a suspension, a ramp, a housing, and a screw. The suspension holds the magnetic head and moves to an unload position. The ramp includes an attachment tab with a through hole. The ramp holds the suspension at the unload position. The housing has a support surface with a screw hole to support the attachment tab. The screw includes a screw head, a screw shaft, and a first contact surface. The screw shaft extends from the screw head in a first direction and is fitted into the screw hole through the through hole. The first contact surface is located on the screw head, tapers in the first direction, and contacts the attachment tab. The screw holds the attachment tab in-between the support surface and the first contact surface.
    Type: Grant
    Filed: March 7, 2023
    Date of Patent: April 9, 2024
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventors: Hisashi Hasegawa, Hideki Yamaguchi, Sinji Tukada
  • Publication number: 20240094756
    Abstract: Provided is a semiconductor device with a reference voltage circuit including an enhancement type transistor having P-type polycrystalline silicon as a first gate electrode, and a depletion type transistor having N-type polycrystalline silicon as a second gate electrode, in which the enhancement type transistor has an impermeable film that is locally provided to cover the first gate electrode via an interlayer insulating film disposed on the first gate electrode, and a nitride film that has an opening portion which is provided larger than the first gate electrode and smaller than the impermeable film, and is provided to cover a periphery of the impermeable film, and the depletion type transistor has a nitride film that is directly provided on an interlayer insulating film disposed on the second gate electrode and covers the depletion type transistor without a gap.
    Type: Application
    Filed: November 10, 2023
    Publication date: March 21, 2024
    Applicant: ABLIC INC.
    Inventors: Takeshi KOYAMA, Hisashi Hasegawa, Shinjiro Kato, Kohei Kawabata
  • Publication number: 20240096353
    Abstract: In general, according to one embodiment, a disk device includes a magnetic disk, a magnetic head, a suspension, a ramp, a housing, and a screw. The suspension holds the magnetic head and moves to an unload position. The ramp includes an attachment tab with a through hole. The ramp holds the suspension at the unload position. The housing has a support surface with a screw hole to support the attachment tab. The screw includes a screw head, a screw shaft, and a first contact surface. The screw shaft extends from the screw head in a first direction and is fitted into the screw hole through the through hole. The first contact surface is located on the screw head, tapers in the first direction, and contacts the attachment tab. The screw holds the attachment tab in-between the support surface and the first contact surface.
    Type: Application
    Filed: March 7, 2023
    Publication date: March 21, 2024
    Inventors: Hisashi HASEGAWA, Hideki YAMAGUCHI, Sinji TUKADA
  • Patent number: 11587869
    Abstract: A semiconductor device includes a semiconductor substrate, a field-effect transistor arranged at least partially on the semiconductor substrate and used in an analog circuit, and having a P-type gate electrode, an interlayer insulating film arranged on the field-effect transistor, and a hydrogen shielding metal or metallic film arranged on the interlayer insulting film and covering the P-type gate electrode and configured to shield hydrogen.
    Type: Grant
    Filed: October 28, 2020
    Date of Patent: February 21, 2023
    Assignee: ABLIC INC.
    Inventors: Hisashi Hasegawa, Takeshi Koyama, Shinjiro Kato, Kohei Kawabata
  • Publication number: 20220137658
    Abstract: Provided is a semiconductor device with a reference voltage circuit including an enhancement type transistor having P-type polycrystalline silicon as a first gate electrode, and a depletion type transistor having N-type polycrystalline silicon as a second gate electrode, in which the enhancement type transistor has an impermeable film that is locally provided to cover the first gate electrode via an interlayer insulating film disposed on the first gate electrode, and a nitride film that has an opening portion which is provided larger than the first gate electrode and smaller than the impermeable film, and is provided to cover a periphery of the impermeable film, and the depletion type transistor has a nitride film that is directly provided on an interlayer insulating film disposed on the second gate electrode and covers the depletion type transistor without a gap.
    Type: Application
    Filed: October 27, 2021
    Publication date: May 5, 2022
    Inventors: Takeshi KOYAMA, Hisashi HASEGAWA, Shinjiro KATO, Kohei KAWABATA
  • Publication number: 20210134714
    Abstract: A semiconductor device includes a semiconductor substrate, a field-effect transistor arranged on the semiconductor substrate and used in an analog circuit, and having a P-type gate electrode, an interlayer insulating film arranged on the field-effect transistor, and a hydrogen shielding metal film arranged on the interlayer insulting film and covering the P-type gate electrode and configured to shield hydrogen.
    Type: Application
    Filed: October 28, 2020
    Publication date: May 6, 2021
    Inventors: Hisashi HASEGAWA, Takeshi KOYAMA, Shinjiro KATO, Kohei KAWABATA
  • Patent number: 10861488
    Abstract: According to one embodiment, a disk device includes a first actuator assembly on a support shaft via a first bearing unit, and a second actuator assembly on the support shaft via a second bearing unit. The first bearing unit includes a first shaft on the support shaft, a first sleeve fixed to the first actuator block, and a bearing between the first shaft and the first sleeve. The second bearing unit includes a second shaft on the support shaft, separated from the first shaft, a second sleeve fixed to the second actuator block, and a bearing between the second shaft and the second sleeve. One axial end of the first shaft faces one axial end of the second shaft.
    Type: Grant
    Filed: August 6, 2019
    Date of Patent: December 8, 2020
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devies & Storage Corporation
    Inventors: Kenji Hayasaka, Hisashi Hasegawa
  • Patent number: 10825482
    Abstract: A magnetic disk device includes a casing having a box-like base that has a bottom wall and a cover that has a first surface facing the bottom wall, a magnetic disk provided in the casing, a head configured to write data to the magnetic disk and to read data from the magnetic disk, an actuator assembly that supports the head in the casing, a conductive container on the first surface of the cover, and a conductive body in contact with the conductive container and the cover.
    Type: Grant
    Filed: September 2, 2019
    Date of Patent: November 3, 2020
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventors: Hirofumi Suzuki, Kouichi Toukairin, Hisashi Hasegawa, Masaya Kudo, Kenji Hayasaka, Yusuke Nojima
  • Publication number: 20200302958
    Abstract: According to one embodiment, a disk device includes a first actuator assembly on a support shaft via a first bearing unit, and a second actuator assembly on the support shaft via a second bearing unit. The first bearing unit includes a first shaft on the support shaft, a first sleeve fixed to the first actuator block, and a bearing between the first shaft and the first sleeve. The second bearing unit includes a second shaft on the support shaft, separated from the first shaft, a second sleeve fixed to the second actuator block, and a bearing between the second shaft and the second sleeve. One axial end of the first shaft faces one axial end of the second shaft.
    Type: Application
    Filed: August 6, 2019
    Publication date: September 24, 2020
    Inventors: Kenji Hayasaka, Hisashi Hasegawa
  • Publication number: 20200286527
    Abstract: A magnetic disk device includes a casing having a box-like base that has a bottom wall and a cover that has a first surface facing the bottom wall, a magnetic disk provided in the casing, a head configured to write data to the magnetic disk and to read data from the magnetic disk, an actuator assembly that supports the head in the casing, a conductive container on the first surface of the cover, and a conductive body in contact with the conductive container and the cover.
    Type: Application
    Filed: September 2, 2019
    Publication date: September 10, 2020
    Inventors: Hirofumi SUZUKI, Kouichi TOUKAIRIN, Hisashi HASEGAWA, Masaya KUDO, Kenji HAYASAKA, Yusuke NOJIMA
  • Patent number: 10475475
    Abstract: A disk apparatus includes recording disks and a first and a second actuator assembly that rotate about a support shaft and that each include: an actuator block; a wiring board having connection terminals and installed on an installation surface of the actuator block; and head assemblies each attached to the actuator block via an arm and each including a head and an interconnection member. The wiring board of each of the first and the second actuator assembly has a connection portion connected to one of the connection terminals and located adjacently to a boundary between the first and the second actuator assembly, and the connection portion of the first or the second actuator assembly is bent with respect to the installation surface.
    Type: Grant
    Filed: August 31, 2018
    Date of Patent: November 12, 2019
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventor: Hisashi Hasegawa
  • Publication number: 20190287558
    Abstract: A disk apparatus includes recording disks and a first and a second actuator assembly that rotate about a support shaft and that each include: an actuator block; a wiring board having connection terminals and installed on an installation surface of the actuator block; and head assemblies each attached to the actuator block via an arm and each including a head and an interconnection member. The wiring board of each of the first and the second actuator assembly has a connection portion connected to one of the connection terminals and located adjacently to a boundary between the first and the second actuator assembly, and the connection portion of the first or the second actuator assembly is bent with respect to the installation surface.
    Type: Application
    Filed: August 31, 2018
    Publication date: September 19, 2019
    Inventor: Hisashi HASEGAWA
  • Patent number: 10297562
    Abstract: Provided is a semiconductor device that is resistant to the corrosion of titanium nitride forming an anti-reflection film. The semiconductor device includes: a wiring layer which includes a wiring film made of aluminum or an aluminum alloy and formed on a substrate and a titanium nitride film formed on the wiring film; a protection layer which covers a top surface and a side surface of the wiring layer; and a pad portion which penetrates the protection layer and the titanium nitride film, and which exposes the wiring film, the protection layer including a first silicon nitride film, an oxide film, and a second silicon nitride film which are layered in the stated order from the side of the wiring layer.
    Type: Grant
    Filed: March 8, 2018
    Date of Patent: May 21, 2019
    Assignee: ABLIC INC.
    Inventors: Kaku Igarashi, Shinjiro Kato, Hisashi Hasegawa, Masaru Akino, Yukihiro Imura
  • Publication number: 20190106485
    Abstract: To provide an antibody against FGF23 and a pharmaceutical composition such as a preventive or therapeutic agent which can prevent or treat by suppressing an action of FGF23 by using the antibody. An antibody or its functional fragment against human FGF23 produced by hybridoma C10 (Accession No. FERM BP-10772).
    Type: Application
    Filed: December 18, 2018
    Publication date: April 11, 2019
    Applicant: KYOWA HAKKO KIRIN CO., LTD.
    Inventors: Yuji Yamazaki, Itaru Urakawa, Hitoshi Yoshida, Yukiko Aono, Takeyoshi Yamashita, Takashi Shimada, Hisashi Hasegawa
  • Patent number: 10202446
    Abstract: To provide an antibody against FGF23 and a pharmaceutical composition such as a preventive or therapeutic agent which can prevent or treat by suppressing an action of FGF23 by using the antibody. An antibody or its functional fragment against human FGF23 produced by hybridoma C10 (Accession No. FERM BP-10772).
    Type: Grant
    Filed: February 10, 2016
    Date of Patent: February 12, 2019
    Assignee: Kyowa Hakko Kirin Co., Ltd.
    Inventors: Yuji Yamazaki, Itaru Urakawa, Hitoshi Yoshida, Yukiko Aono, Takeyoshi Yamashita, Takashi Shimada, Hisashi Hasegawa
  • Publication number: 20180269270
    Abstract: A semiconductor device includes: a bleeder resistor circuit element including a plurality of polycrystalline silicon resistor units; a first metal film divided into a plurality of films so as to individually cover the plurality of polycrystalline silicon resistor units; an integral second metal film for covering an entirety of the bleeder resistor circuit element; and a silicon nitride film formed above the second metal film. Each of the plurality of films of the first metal film includes a first part for covering an electrode portion of the polycrystalline silicon resistor unit, and a second part for covering a portion other than the electrode portion. The first part is electrically connected to the polycrystalline silicon resistor unit.
    Type: Application
    Filed: March 8, 2018
    Publication date: September 20, 2018
    Inventor: Hisashi HASEGAWA
  • Publication number: 20180269170
    Abstract: Provided is a semiconductor device that is resistant to the corrosion of titanium nitride forming an anti-reflection film. The semiconductor device includes: a wiring layer which includes a wiring film made of aluminum or an aluminum alloy and formed on a substrate and a titanium nitride film formed on the wiring film; a protection layer which covers a top surface and a side surface of the wiring layer; and a pad portion which penetrates the protection layer and the titanium nitride film, and which exposes the wiring film, the protection layer including a first silicon nitride film, an oxide film, and a second silicon nitride film which are layered in the stated order from the side of the wiring layer.
    Type: Application
    Filed: March 8, 2018
    Publication date: September 20, 2018
    Inventors: Kaku IGARASHI, Shinjiro KATO, Hisashi HASEGAWA, Masaru AKINO, Yukihiro IMURA
  • Patent number: 9972625
    Abstract: Provided is a semiconductor integrated circuit device including a first N-channel type high withstanding-voltage MOS transistor and a second N-channel type high withstanding-voltage MOS transistor formed on an N-type semiconductor substrate, the first N-channel type high withstanding-voltage transistor including a third N-type low-concentration impurity region containing arsenic having a depth smaller than a P-type well region in a drain region within the P-type well region, and the second N-channel type high withstanding-voltage MOS transistor including a fourth N-type low-concentration impurity region that is adjacent to the P-type well region and has a bottom surface being in contact with the N-type semiconductor substrate. In this manner, the high withstanding-voltage NMOS transistors capable of operating at 30 V or higher are integrated on the N-type semiconductor substrate.
    Type: Grant
    Filed: May 18, 2017
    Date of Patent: May 15, 2018
    Assignee: SII Semiconductor Corporation
    Inventors: Hirofumi Harada, Keisuke Uemura, Hisashi Hasegawa, Shinjiro Kato, Hideo Yoshino
  • Publication number: 20170256545
    Abstract: Provided is a semiconductor integrated circuit device including a first N-channel type high withstanding-voltage MOS transistor and a second N-channel type high withstanding-voltage MOS transistor formed on an N-type semiconductor substrate, the first N-channel type high withstanding-voltage transistor including a third N-type low-concentration impurity region containing arsenic having a depth smaller than a P-type well region in a drain region within the P-type well region, and the second N-channel type high withstanding-voltage MOS transistor including a fourth N-type low-concentration impurity region that is adjacent to the P-type well region and has a bottom surface being in contact with the N-type semiconductor substrate. In this manner, the high withstanding-voltage NMOS transistors capable of operating at 30 V or higher are integrated on the N-type semiconductor substrate.
    Type: Application
    Filed: May 18, 2017
    Publication date: September 7, 2017
    Inventors: Hirofumi HARADA, Keisuke UEMURA, Hisashi HASEGAWA, Shinjiro KATO, Hideo YOSHINO
  • Patent number: 9698147
    Abstract: A semiconductor integrated circuit device has a first N-channel type high withstanding-voltage MOS transistor and a second N-channel type high withstanding-voltage MOS transistor formed on an N-type semiconductor substrate. The first N-channel type high withstanding-voltage transistor includes a third N-type low-concentration impurity region containing arsenic having a depth smaller than a P-type well region in a drain region within the P-type well region, and the second N-channel type high withstanding-voltage MOS transistor includes a fourth N-type low-concentration impurity region that is adjacent to the P-type well region and has a bottom surface in contact with the N-type semiconductor substrate. In this manner, the high withstanding-voltage NMOS transistors are capable of operating at 30 V or higher and are integrated on the N-type semiconductor substrate.
    Type: Grant
    Filed: February 23, 2016
    Date of Patent: July 4, 2017
    Assignee: SII Semiconductor Corporation
    Inventors: Hirofumi Harada, Keisuke Uemura, Hisashi Hasegawa, Shinjiro Kato, Hideo Yoshino