Patents by Inventor Hisashi Hasunuma

Hisashi Hasunuma has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor device having a switch circuit
    Patent number: 7078824
    Abstract: A semiconductor device includes a semiconductor chip, a plurality of bonding pads which are formed on a main surface of the semiconductor chip and include first power source bonding pads, second power source bonding pads and a plurality of signal bonding pads, a plurality of leads which are arranged around the semiconductor chip and include first power source leads and a plurality of signal leads, a plurality of bonding wires which include first bonding wires for connecting the first power source bonding pads with the first power source leads, second bonding wires for connecting the first bonding pads with second bonding pads and third bonding wires for connecting the plurality of signal bonding pads with the plurality of signal leads, and a sealing body which seals the semiconductor chip, the plurality of bonding wires and some of the plurality of leads.
    Type: Grant
    Filed: August 16, 2005
    Date of Patent: July 18, 2006
    Assignees: Renesas Technology Corp., Renesas Northern Japan Semiconductor, Inc.
    Inventors: Yoshihiko Shimanuki, Hisashi Hasunuma
  • Semiconductor device having a switch circuit
    Publication number: 20060060965
    Abstract: A semiconductor device includes a semiconductor chip, a plurality of bonding pads which are formed on a main surface of the semiconductor chip and include first power source bonding pads, second power source bonding pads and a plurality of signal bonding pads, a plurality of leads which are arranged around the semiconductor chip and include first power source leads and a plurality of signal leads, a plurality of bonding wires which include first bonding wires for connecting the first power source bonding pads with the first power source leads, second bonding wires for connecting the first bonding pads with second bonding pads and third bonding wires for connecting the plurality of signal bonding pads with the plurality of signal leads, and a sealing body which seals the semiconductor chip, the plurality of bonding wires and some of the plurality of leads.
    Type: Application
    Filed: August 16, 2005
    Publication date: March 23, 2006
    Inventors: Yoshihiko Shimanuki, Hisashi Hasunuma
  • Semiconductor device
    Patent number: 6930380
    Abstract: A semiconductor device includes a semiconductor chip, a plurality of bonding pads which are formed on a main surface of the semiconductor chip and include first power source bonding pads, second power source bonding pads and a plurality of signal bonding pads, a plurality of leads which are arranged around the semiconductor chip and include first power source leads and a plurality of signal leads, a plurality of bonding wires which include first bonding wires for connecting the first power source bonding pads with the first power source leads, second bonding wires for connecting the first bonding pads with second bonding pads and third bonding wires for connecting the plurality of signal bonding pads with the plurality of signal leads, and a sealing body which seals the semiconductor chip, the plurality of bonding wires and some of the plurality of leads.
    Type: Grant
    Filed: June 4, 2004
    Date of Patent: August 16, 2005
    Assignees: Renesas Technology Corp., Renesas Northern Japan Semiconductor, Inc.
    Inventors: Yoshihiko Shimanuki, Hisashi Hasunuma
  • Semiconductor device
    Publication number: 20040245622
    Abstract: A semiconductor device includes a semiconductor chip, a plurality of bonding pads which are formed on a main surface of the semiconductor chip and include first power source bonding pads, second power source bonding pads and a plurality of signal bonding pads, a plurality of leads which are arranged around the semiconductor chip and include first power source leads and a plurality of signal leads, a plurality of bonding wires which include first bonding wires for connecting the first power source bonding pads with the first power source leads, second bonding wires for connecting the first bonding pads with second bonding pads and third bonding wires for connecting the plurality of signal bonding pads with the plurality of signal leads, and a sealing body which seals the semiconductor chip, the plurality of bonding wires and some of the plurality of leads.
    Type: Application
    Filed: June 4, 2004
    Publication date: December 9, 2004
    Inventors: Yoshihiko Shimanuki, Hisashi Hasunuma