Abstract: A clock recovery circuit having a feedback system in a .pi./4 shift QPSK demodulator, comprising a signal state transition detector for detecting state transitions between consecutive symbols of the demodulated baseband signal which is formed from the detected baseband signal by .pi./4 reverse shifting. According to degree of the detected symbol state transition, the 1/2-symbol delayed baseband signal is shifted by the amount of .pi./8 in phase. According to direction of the detected symbol state transition, the .pi./8 phase shifted baseband signal is converted into an error signal in use for the feedback system. An oscillator generates a clock signal of a frequency controlled by the error signal such that the error signal is reduced in the feedback system.

Abstract: A non-coherent demodulator 1 multiplies a modulated intermediate frequency (IF) signal with a signal from a local oscillator 2 to produce a first pseudo baseband signal having frequency error. The first pseudo baseband signal is supplied to a wide band PLL type demodulator 15. A low-pass filter 26 removes noise component from a first control signal from a loop filter 19 in the wide band PLL type demodulator 15 to produce a second control signal. Multipliers 24 and 25 multiply the first pseudo baseband signal with an output of a voltage-controlled oscillator 27 controlled by the second control signal to produce a second pseudo baseband signal having smaller frequency error. The second pseudo baseband signal is supplied to a narrow band demodulator 14 and converted into a baseband signal.