Patents by Inventor Hisashi Kaziwara
Hisashi Kaziwara has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 6697070Abstract: A graphic processing system has a processor for managing a display area and a character font area both include within an are disposed in the address space. From coded information indicative of a character transferred through a data bus of the system, the processor generates an address at which a character font pattern of the corresponding character has been stored and transfers that character font pattern to a predetermined position on the display area. The graphic processing system realizes high speed development of fonts.Type: GrantFiled: December 7, 1999Date of Patent: February 24, 2004Assignees: Renesas Technology Corporation, Hitachi Engineering Co., Ltd.Inventors: Koyo Katsura, Shigeru Matsuo, Shigeaki Yoshida, Hiroshi Takeda, Hisashi Kaziwara
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Patent number: 6538653Abstract: A graphic processing system has a processor for managing a display area and a character font area both included within an address space. From coded information indicative of a character transferred through a data bus of the system, the processor generates an address at which a character font pattern of the corresponding character has been stored and transfers that character font pattern to a predetermined position on the display area. The graphic processing system realizes high speed development of fonts.Type: GrantFiled: April 1, 1996Date of Patent: March 25, 2003Assignees: Hitachi, Ltd., Hitachi Engineering Co., Ltd.Inventors: Koyo Katsura, Shigeru Matsuo, Shigeaki Yoshida, Hiroshi Takeda, Hisashi Kaziwara
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Patent number: 5956263Abstract: A multiplication, division and square root extraction apparatus which calculates the solutions to addition, division and square root extraction functions by approximation using iteration has a multiplier, an adder-subtracter and a shifter of prescribed bit width connected to a bus. Iteration is conducted by inputting the output of the multiplier to the adder-subtracter or the shifter and returning the result to the input of the multiplier via the bus. A shifter and an arithmetic and logic unit connected to a second bus connected to the aforesaid bus via a switch have a greater bit width than the prescribed bit width and are used for large scale calculations, thus preventing a reduction in processing speed.Type: GrantFiled: January 31, 1997Date of Patent: September 21, 1999Assignees: Hitachi, Ltd., Hitachi Engineering Co., Ltd.Inventors: Masahisa Narita, Hisashi Kaziwara, Takeshi Asai, Shigeki Morinaga, Hiroyuki Kida, Mitsuru Watabe, Tetsuaki Nakamikawa, Shunpei Kawasaki, Junichi Tatezaki, Norio Nakagawa, Yugo Kashiwagi
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Patent number: 5751930Abstract: A graphic processing system for text display which includes a data processing unit, composed of a memory and a processing unit, for creating character code information, and a graphic data processing unit, composed of a graphic data processor and a frame buffer, for creating pixel information. The text display is performed by creating character code information in the data processing unit, supplying the character code information from the data processing unit to the graphic data processor, creating addresses on the frame buffer corresponding to the character code information by the graphic data processor, reading out a character font from a second area of the frame buffer using the created addresses, writing the read-out character font in a predetermined position of a first area of the frame buffer, and outputting the display data at the first area of the frame buffer to a display unit.Type: GrantFiled: March 16, 1994Date of Patent: May 12, 1998Assignees: Hitachi, Ltd., Hitachi Engineering Co., Ltd.Inventors: Koyo Katsura, Shigeru Matsuo, Shigeaki Yoshida, Hiroshi Takeda, Hisashi Kaziwara
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Patent number: 5631858Abstract: A multiplication, division and square root extraction apparatus which calculates the solutions to addition, division and square root extraction functions by approximation using iteration has a multiplier, an adder-subtracter and a shifter of prescribed bit width connected to a bus. Iteration is conducted by inputting the output of the multiplier to the adder-subtracter or the shifter and returning the result to the input of the multiplier via the bus. A shifter and an arithmetic and logic unit connected to a second bus connected to the aforesaid bus via a switch have a greater bit width than the prescribed bit width and are used for large scale calculations, thus preventing a reduction in processing speed.Type: GrantFiled: August 12, 1993Date of Patent: May 20, 1997Assignees: Hitachi, Ltd., Hitachi Engineering Co., Ltd.Inventors: Masahisa Narita, Hisashi Kaziwara, Takeshi Asai, Shigeki Morinaga, Hiroyuki Kida, Mitsuru Watabe, Tetsuaki Nakamikawa, Shunpei Kawasaki, Junichi Tatezaki, Norio Nakagawa, Yugo Kashiwagi
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Patent number: 5504912Abstract: The interface portion of a coprocessor is provided with a FIFO (First-In First-Out) buffer and means for accepting instructions in succession. Pipeline control of the instructions becomes possible in this way, and protocol means associated with a microprocessor is also provided.Type: GrantFiled: February 5, 1992Date of Patent: April 2, 1996Assignees: Hitachi, Ltd., Hitachi Engineering Co., Ltd.Inventors: Shigeki Morinaga, Norio Nakagawa, Mitsuru Watabe, Mamoru Ohba, Hiroyuki Kida, Hisashi Kaziwara, Takeshi Asai, Junichi Tatezaki
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Patent number: 5293558Abstract: A multiplication, division and square root extraction apparatus which calculates the solutions to addition, division and square root extraction functions by approximation using iteration has a multiplier, an adder-subtracter and a shifter of prescribed bit width connected to a bus. Iteration is conducted by inputting the output of the multiplier to the adder-subtracter or the shifter and returning the result to the input of the multiplier via the bus. A shifter and an arithmetic and logic unit connected to a second bus connected to the aforesaid bus via a switch have a greater bit width than the prescribed bit width and are used for large scale calculations, thus preventing a reduction in processing speed.Type: GrantFiled: July 3, 1990Date of Patent: March 8, 1994Assignees: Hitachi, Ltd, Hitachi Engineering Co., Ltd.Inventors: Masahisa Narita, Hisashi Kaziwara, Takeshi Asai, Shigeki Morinaga, Hiroyuki Kida, Mitsuru Watabe, Tetsuaki Nakamikawa, Shunpei Kawasaki, Junichi Tatezaki, Norio Nakagawa, Yugo Kashiwagi
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Patent number: 5125095Abstract: A microcomputer system has a microprocessor and a number of independent coprocessors for executing individual instructions according to instruction data sent from the microprocessor. An address bus and a data bus interconnect the coprocessors with the microprocessor. The microprocessor sends instruction data to the coprocessors via the data bus and concurrently sends coprocessor designation data to the coprocessors via the address bus. The coprocessor designated by the designation data reads and reacts to the instruction data while the other coprocessors within the system disregard the instruction data.Type: GrantFiled: March 28, 1991Date of Patent: June 23, 1992Assignees: Hitachi Microcomputer Engineering Ltd., Hitachi, Ltd., Hitachi Engineering Co., Ltd.Inventors: Takuichiro Nakazawa, Makoto Hanawa, Atsushi Hasegawa, Ikuya Kawasaki, Kazuhiko Iwasaki, Shigeki Morinaga, Hisashi Kaziwara, Takeshi Asai, Junichi Tatezaki
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Patent number: 4947342Abstract: A graphic processing system has a processor for managing a display area and a character font area both included within an address space. From coded information indicative of a character transferred through a data bus of the system, the processor generates an address at which a character font pattern of the corresponding character has been stored and transfers that character font pattern to a predetermined position on the display area. The graphic processing system realizes high speed development of fonts.Type: GrantFiled: September 9, 1986Date of Patent: August 7, 1990Assignees: Hitachi, Ltd., Hitachi Engineering Co., Ltd.Inventors: Koyo Katsura, Shigeru Matsuo, Shigeaki Yoshida, Hiroshi Takeda, Hisashi Kaziwara