Patents by Inventor Hisashi Nakatsuka

Hisashi Nakatsuka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9097689
    Abstract: An apparatus for generating throughput information of a sample analyzer is disclosed. Specifically, this apparatus generates throughput information of a sample analyzer capable of measuring a sample on a plurality of measurement items in which measurement time differs from each other. The apparatus receives an input of a plurality of measurement orders, wherein a measurement order includes a designation of at least one measurement item, generates the throughput information of the sample analyzer based on the received plurality of measurement orders; and outputs the generated throughput information.
    Type: Grant
    Filed: June 29, 2011
    Date of Patent: August 4, 2015
    Assignee: SYSMEX CORPORATION
    Inventors: Takashi Yamato, Hisashi Nakatsuka, Hiroshi Kurono
  • Publication number: 20120004857
    Abstract: An apparatus for generating throughput information of a sample analyzer is disclosed. Specifically, this apparatus generates throughput information of a sample analyzer capable of measuring a sample on a plurality of measurement items in which measurement time differs from each other. The apparatus receives an input of a plurality of measurement orders, wherein a measurement order includes a designation of at least one measurement item, generates the throughput information of the sample analyzer based on the received plurality of measurement orders; and outputs the generated throughput information.
    Type: Application
    Filed: June 29, 2011
    Publication date: January 5, 2012
    Inventors: Takashi Yamato, Hisashi Nakatsuka, Hiroshi Kurono
  • Publication number: 20040191697
    Abstract: The present invention provides a processing method for suppressing variation in the characteristics of a Josephson junction using a niobium type thin film. In the processing method of the present invention, CF4 gas to which CHF3 gas has been added is used as the etching gas in reactive ion etching. As a result, the etching rate is lowered so that high-precision etching control is facilitated. In addition, it is desirable that magnesium oxide is used as mask of this etching, because etching amount of the mask become reduced. In the superconducting integrated circuit manufacturing method of the present invention, the processing method of the present invention is used to process the counter-electrode of a Josephson junction. As a result, variation in the junction area can be reduced; accordingly, variation in the characteristics of the Josephson junction can be reduced.
    Type: Application
    Filed: March 24, 2003
    Publication date: September 30, 2004
    Applicant: Communications Research Laboratory
    Inventors: Hisashi Nakatsuka, Hirotaka Terai, Zhen Wang