Patents by Inventor Hisashi Sakaue

Hisashi Sakaue has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5753944
    Abstract: A semiconductor device having a butting-contact structure for stabilized contact resistance is disclosed. The semiconductor device includes, in the same number, PN regions each having a source region and a diffusion layer in the order with respect to a Y-axis positive direction and PN regions each having a source region and a diffusion layer placed reverse thereto. MOSFET elements have an identical shape in their PN contacts. The interval of the PN contacts is determined equivalent to the interval of boundary lines of the ON regions. The PN contacts are provided such that their centers substantially align with respective boundary lines of the PN regions. Therefore, even when deviation occurs between the PN region and the PN contact along the Y-axis direction, there is provided a equivalency between the sum of areas of the source contact and the sum of areas of the diffusion layer contacts throughout the device.
    Type: Grant
    Filed: July 3, 1996
    Date of Patent: May 19, 1998
    Assignee: Rohm Co. Ltd.
    Inventor: Hisashi Sakaue
  • Patent number: 5406112
    Abstract: A method for producing a semiconductor device includes a step of patterning a surface of a semiconductor substrate of first conductivity-type, a step of injecting impurity ion of second conductivity-type, a step of forming a buried well by subjecting the injected substrate to a thermal treatment, a step of forming a semiconductor crystal layer of the second conductivity-type on the substate surface, and a step of forming semiconductor elements. A semiconductor device and a longitudinal transistor produced by the method are also disclosed. In the method, after the step of forming the semiconductor crystal layer, the impurity concentration of the buried well is controlled to be nearly the same as that of the semiconductor crystal layer. According to the present invention, a semiconductor crystal layer of reverse conductivity-type to that of the substrate can be formed on the substrate in different thickness at different regions.
    Type: Grant
    Filed: September 2, 1994
    Date of Patent: April 11, 1995
    Assignee: Rohm, Co., Ltd.
    Inventor: Hisashi Sakaue
  • Patent number: 5347156
    Abstract: A lateral transistor includes a semiconductor substrate, a buried layer formed on the semiconductor substrate, an epitaxial layer formed on the buried layer in such a manner that the epitaxial layer is a p-type or n-type (first conductivity-type), a diffusion zone having a second conductivity-type opposite to the first conductivity-type and including an emitter zone and collector zone formed on the epitaxial layer, and a base zone. The base zone includes an epitaxial layer interposed between the emitter zone and the collector zone. The collector zone is formed within a well zone in such a manner that the well zone has the same type conductivity as the collector zone and a lower concentration than the collector zone.
    Type: Grant
    Filed: June 18, 1992
    Date of Patent: September 13, 1994
    Assignee: Rohm Co., Ltd.
    Inventor: Hisashi Sakaue