Patents by Inventor Hisashi Sugiyama

Hisashi Sugiyama has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220223941
    Abstract: A battery unit disclosed herein includes a cell stack, bus bars, a cooler, and a heat transfer member. The cell stack includes a first surface and a second surface opposite to the first surface. The cooler includes a cooling surface that faces the second surface of the cell stack to cool the cell stack. The heat transfer member is arranged between the second surface of the cell stack and the cooling surface of the cooler to transfer heat of the cell stack to the cooler. The cooling surface of the cooler has a flat shape. The heat transfer member includes a plurality of bands extending along a stacking direction. The bands are located away from each other. At least one of the bands at least partially overlaps each of electrodes of a plurality of battery cells when viewed in a direction orthogonal to the cooling surface.
    Type: Application
    Filed: November 12, 2021
    Publication date: July 14, 2022
    Applicants: TOYOTA JIDOSHA KABUSHIKI KAISHA, SUBARU CORPORATION
    Inventors: Hisashi Sugiyama, Wataru Kubo, Ryota Aoki, Masatoshi Hiyoshi, Haruka Tsuruta
  • Patent number: 10045556
    Abstract: A dried noodle having a porosity in a cross-sectional area of the noodle of from 0.1 to 15%, a unit porosity in the cross-sectional area of the noodle of from 0.01 to 1%, a gelatinization degree of 30 to 75% and a porous structure, the dried noodle being produced by a process including (a) preparing a noodle dough comprising a main raw material, water and a powder oil, which is entirely derived from an oil, in an amount of more than 0.5% by weight and less than 6% by weight with respect to a total weight of the main raw material, (b) forming a raw noodle body from the noodle dough, and (c) subjecting the raw noodle body to an airflow at a temperature of 90 to 150° C. to evaporate the water, thereby foaming, drying and gelatinizing the raw noodle body, wherein the entire process does not include steaming.
    Type: Grant
    Filed: March 7, 2017
    Date of Patent: August 14, 2018
    Assignee: TOYO SUISAN KAISHA, LTD.
    Inventors: Junya Kanayama, Hisashi Sugiyama, Masafumi Yamakoshi, Taku Ogura
  • Patent number: 9826765
    Abstract: Provided is a dried noodle having a porosity in the cross-sectional area of the noodle of from 0.1 to 15%, a unit porosity in the cross-sectional area of the noodle of from 0.01 to 1%, a gelatinization degree of 30 to 75% and a porous structure.
    Type: Grant
    Filed: December 27, 2012
    Date of Patent: November 28, 2017
    Assignee: TOYO SUISAN KAISHA, LTD.
    Inventors: Junya Kanayama, Hisashi Sugiyama, Masafumi Yamakoshi, Taku Ogura
  • Publication number: 20170172188
    Abstract: A dried noodle having a porosity in a cross-sectional area of the noodle of from 0.1 to 15%, a unit porosity in the cross-sectional area of the noodle of from 0.01 to 1%, a gelatinization degree of 30 to 75% and a porous structure, the dried noodle being produced by a process including (a) preparing a noodle dough comprising a main raw material, water and a powder oil, which is entirely derived from an oil, in an amount of more than 0.5% by weight and less than 6% by weight with respect to a total weight of the main raw material, (b) forming a raw noodle body from the noodle dough, and (c) subjecting the raw noodle body to an airflow at a temperature of 90 to 150° C. to evaporate the water, thereby foaming, drying and gelatinizing the raw noodle body, wherein the entire process does not include steaming.
    Type: Application
    Filed: March 7, 2017
    Publication date: June 22, 2017
    Applicant: Toyo Suisan Kaisha, Ltd.
    Inventors: Junya KANAYAMA, Hisashi SUGIYAMA, Masafumi YAMAKOSHI, Taku OGURA
  • Publication number: 20140099695
    Abstract: An object of the present invention is to enable simpler operation in real time and culture while removing unnecessary cells from cultured cells for purification in analyzing, fractionating, and culturing the cells alive and to analyze and fractionate desired cells from the cultured cells to increase the purity, recovery rate, and viability of the cells. The present invention employs a cell-adhesive photocontrollable base material, wherein light irradiation causes the bond dissociation of a photolabile group comprising a coumarinylmethyl skeleton to produce the separation of a cell-adhesive material to leave a non-cell-adhesive material. As a result, cell images can be detected and analyzed to obtain the positional information of desired cells. Based on the positional information thus obtained, the cells can be analyzed and fractionated alive.
    Type: Application
    Filed: April 11, 2012
    Publication date: April 10, 2014
    Applicants: HITACHI HIGH-TECHNOLOGIES CORPORATION, TOHO UNIVERSITY
    Inventors: Toshiaki Furuta, Akinobu Suzuki, Hisashi Sugiyama, Satoshi Ozawa, Hiroko Tada
  • Publication number: 20140011960
    Abstract: In analyzing, fractionating, and culturing cells alive, operations can be more simply made in real time and culture can be performed while removing unnecessary cells from cultured cells for purification. Desired cells are also analyzed and fractionated from the cultured cells to increase the purity, recovery rate, and viability of the cells. A cell-adhesive photocontrollable base material is used in which light irradiation causes the bond dissociation of a photolabile group comprising an O-nitrobenzyl skeleton to irreversibly change the surface of the irradiated portion thereof from that of the cell-adhesive material to that of a non-cell-adhesive material. Cell images are detected and analyzed to obtain the positional information of desired cells. Based on this information, areas among cells and a cell-adhesive photocontrollable material are cut by second light irradiation.
    Type: Application
    Filed: February 6, 2012
    Publication date: January 9, 2014
    Inventors: Tomohiro Konno, Kazuhiko Ishihara, Batzaya Byambaa, Hisashi Sugiyama, Satoshi Ozawa
  • Publication number: 20130115359
    Abstract: Provided is a dried noodle having a porosity in the cross-sectional area of the noodle of from 0.1 to 15%, a unit porosity in the cross-sectional area of the noodle of from 0.01 to 1%, a gelatinization degree of 30 to 75% and a porous structure.
    Type: Application
    Filed: December 27, 2012
    Publication date: May 9, 2013
    Applicant: TOYO SUISAN KAISHA, LTD.
    Inventors: Junya KANAYAMA, Hisashi SUGIYAMA, Masafumi YAMAKOSHI, Taku OGURA
  • Publication number: 20120225448
    Abstract: When cells are analyzed, fractionated, and incubated while keeping the cells alive, real-time operations can be performed more easily and the cells can be incubated while removing unnecessary cells from the incubated cells to purify the cells being incubated. Furthermore, desired cells are separated through analysis from the incubated cells, and the purity, recovery, and viability of the cells are heightened. Use is made of a substrate having photo-controllable cell adhesion properties, the substrate comprising a transparent base and, formed thereon, a film of a material which has photo-controllable cell adhesion properties and has been obtained by bonding a cell-adhesive material to a cell-non-adhesive material through photo-dissociable groups. Cell images are detected and analyzed to obtain information about the location of desired cells.
    Type: Application
    Filed: November 4, 2010
    Publication date: September 6, 2012
    Applicant: Hitachi High-Technologies Corporation
    Inventors: Hisashi Sugiyama, Satoshi Takahashi, Kenko Uchida, Satoshi Ozawa
  • Publication number: 20040265543
    Abstract: A resin-molded product has a surface formed with a patterned shape imitative of natural leather and its surface shape is formed so as to satisfy glossiness Gs (60°) in a value greater than 0% and equal to or less than 2.7% and to have a microscopic convexoconcave with an absolute value equal to or greater than 1.2 and equal to or less than 3.0 on a gradient SC of a straight line intersecting two points at 100% and 50% in a cutting level of a bearing curve corresponding to a roughness curve.
    Type: Application
    Filed: April 23, 2004
    Publication date: December 30, 2004
    Inventors: Motoru Komatsu, Hisashi Sugiyama, Yuuko Maruse, Takashi Takeuchi
  • Patent number: 5539223
    Abstract: A semicustom integrated circuit comprises pads arranged on peripheral portions of a chip along the four sides thereof. Peripheral circuit cells are arranged on a part of the chip to the inside of the pads. An internal circuit is arranged on a part of the chip to the inside of the peripheral circuit cell. The peripheral circuit cells include an ECL level input circuit an ECL level output circuit, a TTL level input circuit and a TTL level output circuit. Main source lines are formed on the peripheral circuit cells so as to surround the internal circuit. The main source lines are connected to pads to which source potentials is applied. Branch source lines cross the main source lines and connected to a selected one of the peripheral circuit cells and said internal circuit. The main source lines are selectively connected to the branch source lines by an interlayer connecting source line.
    Type: Grant
    Filed: March 25, 1993
    Date of Patent: July 23, 1996
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takeshi Sugoh, Hisashi Sugiyama
  • Patent number: 5480048
    Abstract: A multilayer wiring board fabricating method and a multilayer wiring board fabricated with use of the method that a solvent-free fluid polymer precursor is put on a wiring layer of a base substrate, and space among the wirings is exhausted and is filled with the precursor, and the precursor is hardened under a hydrostatic pressure and then the next wiring layer is formed before the above process is repeated one or more times. The multilayer wiring board fabricating method is excellent in the mass productivity and low cost and in that the wiring can be made highly dense with the substrate having vertical via conductors for connection among the conductor layers.
    Type: Grant
    Filed: August 30, 1993
    Date of Patent: January 2, 1996
    Assignee: Hitachi, Ltd.
    Inventors: Naoya Kitamura, Hisashi Sugiyama, Yoshihide Yamaguchi, Masayuki Kyoui, Hideyasu Murooka, Ryoji Iwamura, Makio Watanabe
  • Patent number: 5264319
    Abstract: Disclosed herein is a photosensitive resin composition composed mainly of an alkali-soluble organometallic polymer and a photosensitive dissolution inhibitor. The composition is used as a positive type resist which can be developed with an alkali developing solution. The resist has high sensitivity, high resolution, and resistance to oxygen plasma.
    Type: Grant
    Filed: June 4, 1992
    Date of Patent: November 23, 1993
    Assignee: Hitachi, Ltd.
    Inventors: Hisashi Sugiyama, Kazuo Nate, Takashi Inoue, Akiko Mizushima
  • Patent number: 5158855
    Abstract: An .alpha.-diazoacetoacetic acid ester derived from cholic acid, deoxycholic acid, lithocholic acid or a derivative thereof is effective as a sensitizer in a photosensitive resin composition containing an alkali-soluble resin to form a resist for lithography using KrF excimer laser.
    Type: Grant
    Filed: September 22, 1988
    Date of Patent: October 27, 1992
    Assignee: Hitachi, Ltd.
    Inventors: Hisashi Sugiyama, Kazuo Nate, Akiko Mizushima, Keisuke Ebata
  • Patent number: 5034630
    Abstract: A logic circuit outputs state signals of seven different kinds, on the basis of first, second and third digital signals. A first composite gate circuit outputs a logical OR among the first to third digital signals as a first state signal. A first gate circuit outputs a logical OR between the second and third digital signals as a second state signal. A second composite gate circuit is supplied with a logical AND between the first and second digital signals, and outputs a logical OR between the supplied logical AND and the third digital signal as third state signal. A third composite gate circuit is supplied with a logical OR between the first and second digital signals, and outputs a logical AND between the supplied logical OR and the third digital signal as a fifth state signal. A second gate circuit outputs a logical AND between the second and third digital signals as a sixth state signal.
    Type: Grant
    Filed: February 7, 1990
    Date of Patent: July 23, 1991
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hisashi Sugiyama, Michinori Nakamura, Yasuhiro Sugimoto
  • Patent number: 4918450
    Abstract: An analog/digital converter circuit including a capacitor having a first end, to which an analog voltage is applied, and a second end, an input buffer circuit having an input terminal, connected to the second end of said capacitor, and an output terminal, a reference voltage generating circuit for generating a plurality of reference voltages having different voltage levels, a voltage comparator circuit having a plurality of voltage comparators for comparing the output voltage of the input buffer circuit with each of the reference voltages generated by the reference voltage generating circuit, and generating a digital signal corresponding to the comparison results, a decoder circuit for decoding the output of the voltage comparator circuit, and D.C. bias voltage selection/supply circuit for selecting one of the reference voltages of the reference voltage generating circuit and supplying the selected reference voltage as a D.C. bias voltage to the input terminal of the input buffer circuit.
    Type: Grant
    Filed: June 19, 1989
    Date of Patent: April 17, 1990
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hisashi Sugiyama, Yasuhiro Sugimoto
  • Patent number: 4798980
    Abstract: A Booth's algorithm conversion circuit having first and second switches controlled by input signals QX and Q2X and receiving as input, signals X.sub.i of a logic level positioned in the i digit order of a multiplicand X and signal X.sub.i-1 of a logic level positioned in the i-1 digit order of multiplicand X. The outputs of the first and second switches are tied together and to ground via first and second transitors controlled by signals QX and Q2X, the first and second transistors conducting in an inverse relationship to the first and second switch circuits. The common output of the first and second switch circuits is input to an exclusive OR circuit which receives an additional logic 1 or logic 0 input signal to produce the Booth's converted output. The resulting number of circuit elements and gates provides a simplified, high speed and small circuit for producing the Booth's conversion.
    Type: Grant
    Filed: May 13, 1987
    Date of Patent: January 17, 1989
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hisashi Sugiyama, Yasuhiro Sugimoto, Yukio Kamatani
  • Patent number: 4779016
    Abstract: Level conversion circuit for converting ECL logic level signals to CMOS logic level signals.
    Type: Grant
    Filed: January 6, 1987
    Date of Patent: October 18, 1988
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hisashi Sugiyama, Yasuhiro Sugimoto
  • Patent number: 4745169
    Abstract: There are provided an alkali-soluble siloxane polymer, an alkali-soluble silmethylene polymer, and an alkali-soluble polyorganosilsesquioxane polymer. They are useful as a photoresist for the fabrication of semiconductor devices. They are suitable for dry etching because of their superior resistance to oxygen plasmas.
    Type: Grant
    Filed: May 5, 1986
    Date of Patent: May 17, 1988
    Assignee: Hitachi, Ltd.
    Inventors: Hisashi Sugiyama, Kazuo Nate, Takashi Inoue, Akiko Mizushima