Abstract: There are disclosed a chamber plate for use in cell fusion comprising a plate of single crystal silicon on which a plurality of chambers for holding at least a pair of unit cells are formed in array, said chamber having at the bottom a plate having slits which do not pass cells to be held; and a process for producing a chamber plate for use in cell fusion which comprises forming chambers for holding cells in a plate of single crystal silicon by anisotropic etching or isotropic etching by chemical etching.

Abstract: A composition for use in yeast-fermented foods to modify the food and improve its softness during storage is disclosed. The composition comprises (by weight) 1 part of protein, 0.5 to 4 parts of edible fat and oil, 3.5 to 13 parts of water, 0.5 to 2 parts of at least one material selected from the group consisting of mashed potato powder, sweet potato powder and starch; and 0.3 to 4.5% of a phosphate and/or citrate based on the total weight of said protein, edible fat and oil, water and at least one material selected from the group consisting of mashed potato powder, sweet potato powder and starch.

Abstract: An analog-to-digital converter comprising a capacitive element for storing an analog input signal, a discharge means for discharging the charge stored in said capacitive element, a means for counting the number of clockpulses between the time of discharge starting and the time at which the voltage at the output of said capacitive element reaches a certain detection level, and a bias voltage supply means for supplying a bias voltage in order to bring the voltage at the output terminal of said capacitive element at the discharge starting time above said detection level.

Abstract: An analog-to-digital converter comprising a capacitor for storing an analog input signal, a constant current discharging circuit coupled with the capacitor for discharging the charge stored therein, a level detection circuit connected to the input terminal of the capacitor, a counter connected to the output terminal of the level detection circuit for counting the number of clock-pulses between the time of discharge start and the time when the voltage at the input terminal of the capacitor drops to a detection level of the level detection circuit, a bias voltage supply means connected in series with the capacitor for adding a bias voltage to the voltage at the input terminal of said capacitor, and a switch connected in parallel with the capacitor for short-circuiting the capacitor when the voltage at the input terminal of said capacitor drops to the detection level.