Abstract: A method of reading out data from nonvolatile semiconductor memory including the steps of applying a first voltage to a bit line contact; applying a second voltage to a source line contact, wherein the second voltage is substantially smaller than the first voltage; applying a third voltage gates of third and fourth select gate transistors, the third voltage configured to bring the third and fourth select gate transistors into conduction; applying a fourth voltage to gates of the plurality of memory cell transistors of a second memory cell unit, the fourth voltage configured to bring the plurality of memory cell transistors of the second memory cell unit into conduction or not, depending on the data that is stored in the memory cell unit; and applying a fifth voltage to gates of the plurality of memory cell transistors of a first memory cell unit, the fifth voltage configured to bring the plurality of memory cell transistors of the first memory cell unit into conduction; wherein the fifth voltage is bigger tha

Abstract: A semiconductor device includes a semiconductor substrate divided into a memory cell region in which a memory cell is formed and a peripheral circuit region in which a peripheral circuit for driving the memory cell is formed, a plurality of conductive layers provided in each region so as to interpose an interlayer insulating film, a plurality of connection wiring layers formed in a plurality of holes which are formed in the interlayer insulating film so as to extend through the conductive layers of each region, the connection wiring layers electrically connecting the conductive layers, and a spacer insulating film functioning as a spacer which is formed on inner sidewall surfaces of the holes and outer sidewall surfaces of the connection wiring layers in each region.

Abstract: A semiconductor device includes a semiconductor substrate, a gate insulating film, gate electrodes, a first silicon oxide film, bit lines formed on the first silicon oxide film and including lower surfaces having respective recesses, a contact plug layer located between the gate electrodes and including a first portion, a second portion having a fourth side surface between the opposed second side surfaces of first silicon oxide film and a third portion having an upper surface and fifth side surfaces embedded in the respective recesses of the bit line, a first silicon nitride layer between a third side surface of the first portion of the contact plug and a first side surface of the gate electrode, and a second silicon oxide film. The entire upper surface and fifth side surface of the third portion of the contact plug directly contact with inner surfaces of the recesses respectively.

Abstract: A method of reading out data from nonvolatile semiconductor memory including the steps of applying a first voltage to a bit line contact; applying a second voltage to a source line contact, wherein the second voltage is substantially smaller than the first voltage; applying a third voltage gates of third and fourth select gate transistors, the third voltage configured to bring the third and fourth select gate transistors into conduction; applying a fourth voltage to gates of the plurality of memory cell transistors of a second memory cell unit, the fourth voltage configured to bring the plurality of memory cell transistors of the second memory cell unit into conduction or not, depending on the data that is stored in the memory cell unit; and applying a fifth voltage to gates of the plurality of memory cell transistors of a first memory cell unit, the fifth voltage configured to bring the plurality of memory cell transistors of the first memory cell unit into conduction; wherein the fifth voltage is bigger tha

Abstract: A nonvolatile semiconductor memory includes memory cell units, each having memory cell transistors aligned in a column direction and capable of writing and erasing electronic data; and contacts on active areas, arranged on both sides of memory cell unit arrays in which the memory cell units are serially connected in the column direction, and the contacts on active areas are shared by the memory cell unit arrays; wherein, the respective memory cell unit arrays are located having a periodical shift length equal to and or more than the integral multiple length of the periodical length of the memory cell units aligned in the column direction so as to be staggered from each other as compared with neighboring memory cell unit arrays aligned in the row direction.

Abstract: In fabrication of a semiconductor device, a first insulating film, electrode film and silicon nitride film sequentially stacked on a semiconductor substrate are etched with the substrate so that a trench is formed. The electrode film is then exposed. A second insulating film buried in the trench is isotropically etched so that an upper side wall of the electrode film is exposed, so that a side end of an upper surface of the insulating film is located between the upper surfaces of the substrate and electrode film and so that a middle upper portion of an upper surface of the second insulating film is higher than the side end and lower than the upper surface of the first electrode film, A third insulating film is formed on the upper surface of the first electrode film so as to entirely cover the upper surface of the second insulating film.

Abstract: A semiconductor device includes a semiconductor substrate including a first upper surface, a first insulating film including an upper portion including a first side wall having a first upper end and a second upper surface having a second upper end, a second insulating film formed on the first upper surface of the substrate, a floating gate electrode including a third upper surface, a second side wall and a lower surface, a third insulating film, and a control gate electrode. A height of the second upper end is lower than a height of the third upper surface and higher than a height of the first upper end relative to the first upper surface. The first upper end is located at a position higher than the lower surface of the floating gate electrode. The entire second side wall is aligned with the first side wall of the first insulating film.

Abstract: A semiconductor device includes a semiconductor substrate divided into a memory cell region in which a memory cell is formed and a peripheral circuit region in which a peripheral circuit for driving the memory cell is formed, a plurality of conductive layers provided in each region so as to interpose an interlayer insulating film, a plurality of connection wiring layers formed in a plurality of holes which are formed in the interlayer insulating film so as to extend through the conductive layers of each region, the connection wiring layers electrically connecting the conductive layers, and a spacer insulating film functioning as a spacer which is formed on inner sidewall surfaces of the holes and outer sidewall surfaces of the connection wiring layers in each region.

Abstract: A nonvolatile semiconductor memory includes memory cell units, each having memory cell transistors aligned in a column direction and capable of writing and erasing electronic data; and contacts on active areas, arranged on both sides of memory cell unit arrays in which the memory cell units are serially connected in the column direction, and the contacts on active areas are shared by the memory cell unit arrays; wherein, the respective memory cell unit arrays are located having a periodical shift length equal to and or more than the integral multiple length of the periodical length of the memory cell units aligned in the column direction so as to be staggered from each other as compared with neighboring memory cell unit arrays aligned in the row direction.

Abstract: A semiconductor device comprising a lower conductive layer, an upper conductive layer located over the lower conductive layer, a first insulating film formed between upper and lower conductive layers, a plurality of connected wiring layers each of which has an upper surface, an upper side face and a sidewall outer periphery, each connected wiring layer being in structural contact with the upper conductive layer at the upper surface thereof and with the lower conductive layer, each connected wiring layer connecting the upper and lower conductive layers to each other, and a second insulating film formed on the sidewall outer periphery of each connected wiring layer so as to serve as a spacer between each connected wiring layer and the adjacent connected wiring layer, the second insulating film being made from a material differing from a material for the first insulating film.

Abstract: A semiconductor device includes a semiconductor substrate having an upper surface, a trench formed in the semiconductor substrate, a first insulating film formed on the semiconductor substrate so as to be located at opposite sides of the trench, a polycrystalline silicon film stacked on the first insulating film, the polycrystalline silicon film having an upper surface, a second insulating film buried in the trench and having an upper surface end located lower than the upper surface of the polycrystalline silicon film and higher than the upper surface of the semiconductor substrate, the second insulating film having a central upper surface located nearer to the upper surface of the polycrystalline silicon film than the upper surface end thereof.

Abstract: A semiconductor device provided with a thin film of 0.1 nm to 2 nm in thickness, having a crystal structure different from that of a conductor and a semiconductor region, between the conductor and the semiconductor region. When the semiconductor region is made of single crystal silicon and the conductor region is made of amorphous silicon or poly silicon, the oxygen surface concentration of the thin film is equal to or higher than 1.times.10.sup.15 cm.sup.-2 and equal to or lower than 4.times.10.sup.15 cm.sup.-2 in one case, that of oxygen is equal to or higher than 1.times.10.sup.15 cm.sup.-2 and equal to or lower than 2.times.10.sup.15 cm.sup.-2 and that of nitrogen is equal to or higher than 1.times.10.sup.15 cm.sup.-2 and equal to or lower than 4.times.10.sup.15 cm.sup.-2 in the other case. The presence of the thin film prevents the epitaxial growth from starting from the interface between the conductor and the semiconductor region and reduces the crystal defect formation and growth near the interface.