Patents by Inventor Hisashi Yamada

Hisashi Yamada has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11982998
    Abstract: A manufacturing monitoring assistance device includes: a model creation unit creating a computation model when a product as a sample is normal, based on a three-dimensional form acquired from the product; a simulation unit creating a corrective computation model when the product is abnormal, by adding a sample of an abnormal portion in the product to the created computation model, and performing a simulation on each of the computation model and the corrective computation model; and a monitoring method determination unit determining a method for monitoring a manufacturing process for the product, based on an abnormality index being a difference between an output from a sensor as a result of the simulation performed on the computation model and an output from a sensor as a result of the simulation performed on the corrective computation model, and causing an output device to display the determined method and the abnormality index.
    Type: Grant
    Filed: January 30, 2020
    Date of Patent: May 14, 2024
    Assignee: HITACHI, LTD.
    Inventors: Masanori Kitaoka, Hisashi Endou, Nobuhiro Kakeno, Hiroshi Yoshikawa, Toshihiro Yamada
  • Publication number: 20240136439
    Abstract: A semiconductor device includes a substrate, a semiconductor layer, an element region, and fin transistors. The substrate includes a principal surface. The semiconductor layer is formed as a surface layer or on the principal surface of the substrate, the surface layer being the principal surface of the substrate. The semiconductor layer has a crystal structure in which an angle between two of crystal orientations with equivalent relationships on a crystal plane having a correspondence with the principal surface of the substrate is 60 degrees or 120 degrees. The element region includes unit element regions formed on the principal surface of the substrate. The fin transistors are formed in the semiconductor layer, in the respective unit element regions. The fin transistors radially extend from a center toward an outer periphery of the element region. Adjacent two of the fin transistors have a spacing with a 60° angle or a 120° angle.
    Type: Application
    Filed: March 22, 2021
    Publication date: April 25, 2024
    Applicant: Mitsubishi Electric Corporation
    Inventors: Yuki TAKIGUCHI, Eiji YAGYU, Kunihiko NISHIMURA, Hisashi SAITO, Takahiro YAMADA, Daisuke TSUNAMI, Marika NAKAMURA, Masanao ITO
  • Patent number: 11947175
    Abstract: The present disclosure intends to facilitate tearing a metal sheath even in a case where the metal sheath is incorporated in an optical fiber cable. The optical fiber cable of the present disclosure includes a cable core arranged at a central portion and accommodating a plurality of optical fibers gathered together, an inner layer sheath arranged on an outer circumference of the cable core and sheathing the cable core, a metal sheath arranged on an outer circumference of the inner layer sheath and wound around the inner layer sheath, an outer layer sheath arranged on an outer circumference of the metal sheath and sheathing the metal sheath, and at least one outer sheath tearing string arranged in a longitudinal direction inside the metal sheath.
    Type: Grant
    Filed: January 31, 2020
    Date of Patent: April 2, 2024
    Assignee: Nippon Telegraph and Telephone Corporation
    Inventors: Yuta Maruo, Hiroaki Tanioka, Hisashi Izumita, Yusuke Yamada, Shigekatsu Tetsutani, Yohei Endo
  • Patent number: 11943243
    Abstract: In an anomaly detection method that determines whether each frame in observation data constituted by a collection of frames sent and received over a communication network system is anomalous, a difference between a data distribution of a feature amount extracted from the frame in the observation data and a data distribution for a collection of frames sent and received over the communication network system, obtained at a different timing from the observation data, is calculated. A frame having a feature amount for which the difference is predetermined value or higher is determined to be an anomalous frame. An anomaly contribution level of feature amounts extracted from the frame determined to be an anomalous frame is calculated, and an anomalous payload part, which is at least one part of the payload corresponding to the feature amount for which the anomaly contribution level is at least the predetermined value, is output.
    Type: Grant
    Filed: May 17, 2021
    Date of Patent: March 26, 2024
    Assignee: PANASONIC INTELLECTUAL PROPERTY CORPORATION OF AMERICA
    Inventors: Takamitsu Sasaki, Tomoyuki Haga, Daiki Tanaka, Makoto Yamada, Hisashi Kashima, Takeshi Kishikawa
  • Publication number: 20240062900
    Abstract: An information processing device according to an embodiment includes a hardware processor coupled to a memory. The hardware processor estimates morbidity representing a probability of a subject being suffering from a specific disease. The morbidity is estimated on the basis of: a first probability model representing a relation between a first physical quantity associated with the specific disease and a second physical quantity to be measured, a second probability model representing a relation between the first physical quantity and information about whether the subject is suffering from the specific disease, a prior probability of morbidity representing a probability of the subject being suffering from the specific disease in a situation where no information has been obtained with respect to the first physical quantity or the second physical quantity related to the subject, and the second physical quantity obtained by measuring the subject.
    Type: Application
    Filed: February 24, 2023
    Publication date: February 22, 2024
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Masaaki TAKADA, Miho SAKO, Hisashi YAMADA
  • Publication number: 20220398358
    Abstract: According to an embodiment, an information processing device includes one or more processors. The one or more processors are configured to: build a prediction model for predicting prediction data for a second region included in a plurality of regions based on acquired data acquired for one or more first regions included in the plurality of regions; and predict the prediction data based on the acquired data by using the prediction model.
    Type: Application
    Filed: February 25, 2022
    Publication date: December 15, 2022
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Lele XI, Arika FUKUSHIMA, Hisashi YAMADA
  • Publication number: 20220343215
    Abstract: An information processing apparatus according to one embodiment includes one or more hardware processors coupled to a memory. The hardware processors function as an acquisition unit, a model generation unit, and a model generation unit. The acquisition unit serves to acquire one or more patterns from among multiple patterns each representing temporal variation of first data being data to be predicted. The patterns are determined for a first region designated out of regions serving as prediction targets of the first data. The model generation unit serves to generate a prediction model for predicting the temporal variation of the first data in the first region. The prediction model is generated on the basis of the acquired patterns. The model generation unit serves to determine a parameter of the prediction model.
    Type: Application
    Filed: February 25, 2022
    Publication date: October 27, 2022
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Arika FUKUSHIMA, Lele XI, Hisashi YAMADA
  • Patent number: 10763332
    Abstract: Provided is a semiconductor wafer in which a nitride crystal layer on a silicon wafer includes a reaction suppressing layer to suppress reaction between a silicon atom and a Group-III atom, a stress generating layer to generate compressive stress and an active layer in which an electronic element is to be formed, the reaction suppressing layer, the stress generating layer and the active layer are arranged in an order of the reaction suppressing layer, the stress generating layer and the active layer with the reaction suppressing layer being positioned the closest to the silicon wafer, and the stress generating layer includes a first crystal layer having a bulk crystal lattice constant of al and a second crystal layer in contact with a surface of the first crystal layer that faces the active layer, where the second crystal layer has a bulk crystal lattice constant of a2 (a1<a2).
    Type: Grant
    Filed: May 4, 2017
    Date of Patent: September 1, 2020
    Assignee: SUMITOMO CHEMICAL COMPANY, LIMITED
    Inventors: Hisashi Yamada, Taiki Yamamoto, Kenji Kasahara
  • Patent number: 9828695
    Abstract: A nonpolar III-nitride film grown on a miscut angle of a substrate, in order to suppress the surface undulations, is provided. The surface morphology of the film is improved with a miscut angle towards an a-axis direction comprising a 0.15° or greater miscut angle towards the a-axis direction and a less than 30° miscut angle towards the a-axis direction.
    Type: Grant
    Filed: April 20, 2016
    Date of Patent: November 28, 2017
    Assignee: THE REGENTS OF THE UNIVERSITY OF CALIFORNIA
    Inventors: Asako Hirai, Zhongyuan Jia, Makoto Saito, Hisashi Yamada, Kenji Iso, Steven P. DenBaars, Shuji Nakamura, James S. Speck
  • Publication number: 20170327969
    Abstract: A nonpolar III-nitride film grown on a miscut angle of a substrate. The miscut angle towards the <000-1> direction is 0.75° or greater miscut and less than 27° miscut towards the <000-1> direction. Surface undulations are suppressed and may comprise faceted pyramids. A device fabricated using the film is also disclosed. A nonpolar III-nitride film having a smooth surface morphology fabricated using a method comprising selecting a miscut angle of a substrate upon which the nonpolar III-nitride films are grown in order to suppress surface undulations of the nonpolar III-nitride films. A nonpolar III-nitride-based device grown on a film having a smooth surface morphology grown on a miscut angle of a substrate which the nonpolar III-nitride films are grown. The miscut angle may also be selected to achieve long wavelength light emission from the nonpolar film.
    Type: Application
    Filed: May 26, 2017
    Publication date: November 16, 2017
    Applicant: The Regents of the University of California
    Inventors: Kenji Iso, Hisashi Yamada, Makoto Saito, Asako Hirai, Steven P. DenBaars, James S. Speck, Shuji Nakamura
  • Publication number: 20170236906
    Abstract: Provided is a semiconductor wafer in which a nitride crystal layer on a silicon wafer includes a reaction suppressing layer to suppress reaction between a silicon atom and a Group-III atom, a stress generating layer to generate compressive stress and an active layer in which an electronic element is to be formed, the reaction suppressing layer, the stress generating layer and the active layer are arranged in an order of the reaction suppressing layer, the stress generating layer and the active layer with the reaction suppressing layer being positioned the closest to the silicon wafer, and the stress generating layer includes a first crystal layer having a bulk crystal lattice constant of al and a second crystal layer in contact with a surface of the first crystal layer that faces the active layer, where the second crystal layer has a bulk crystal lattice constant of a2 (a1<a2).
    Type: Application
    Filed: May 4, 2017
    Publication date: August 17, 2017
    Applicant: SUMITOMO CHEMICAL COMPANY, LIMITED
    Inventors: Hisashi YAMADA, Taiki YAMAMOTO, Kenji KASAHARA
  • Publication number: 20160230312
    Abstract: A nonpolar III-nitride film grown on a miscut angle of a substrate, in order to suppress the surface undulations, is provided. The surface morphology of the film is improved with a miscut angle towards an ?-axis direction comprising a 0.15° or greater miscut angle towards the ?-axis direction and a less than 30° miscut angle towards the ?-axis direction.
    Type: Application
    Filed: April 20, 2016
    Publication date: August 11, 2016
    Applicant: THE REGENTS OF THE UNIVERSITY OF CALIFORNIA
    Inventors: Asako Hirai, Zhongyuan Jia, Makoto Saito, Hisashi Yamada, Kenji Iso, Steven P. DenBaars, Shuji Nakamura, James S. Speck
  • Patent number: 9340899
    Abstract: A nonpolar III-nitride film grown on a miscut angle of a substrate, in order to suppress the surface undulations, is provided. The surface morphology of the film is improved with a miscut angle towards an a-axis direction comprising a 0.15° or greater miscut angle towards the a-axis direction and a less than 30° miscut angle towards the a-axis direction.
    Type: Grant
    Filed: June 16, 2014
    Date of Patent: May 17, 2016
    Assignee: The Regents of the University of California
    Inventors: Asako Hirai, Zhongyuan Jia, Makoto Saito, Hisashi Yamada, Kenji Iso, Steven P. DenBaars, Shuji Nakamura, James S. Speck
  • Patent number: 9112035
    Abstract: A semiconductor substrate includes a substrate, an insulating layer, and a semiconductor layer. The insulating layer is over and in contact with the substrate. The insulating layer includes at least one of an amorphous metal oxide and an amorphous metal nitride. The semiconductor layer is over and in contact with the insulating layer. The semiconductor layer is formed by crystal growth.
    Type: Grant
    Filed: March 2, 2012
    Date of Patent: August 18, 2015
    Assignees: SUMITOMO CHEMICAL COMPANY, LIMITED, THE UNIVERSITY OF TOKYO, NATIONAL INSTITUTE OF ADVANCED INDUSTRIAL SCIENCE AND TECHNOLOGY
    Inventors: Hisashi Yamada, Masahiko Hata, Masafumi Yokoyama, Mitsuru Takenaka, Shinichi Takagi, Tetsuji Yasuda, Hideki Takagi, Yuji Urabe
  • Publication number: 20150199382
    Abstract: A related content retrieval device that can retrieve a wide variety of related contents. The related content retrieval device includes: an input unit for implementing input of a content; a metadata acquisition unit for acquiring metadata of the content input by the input unit; a posted text acquisition unit for acquiring a posted text related to the metadata acquired by the metadata acquisition unit, from a posting server accumulating user posted texts; a related content acquisition unit for acquiring a related content related to the posted text acquired by the posted text acquisition unit, from a retrieval server capable of retrieving a content on a network device; and an output unit for outputting the related content acquired by the related content acquisition unit.
    Type: Application
    Filed: May 8, 2013
    Publication date: July 16, 2015
    Applicant: NTT DOCOMO, INC.
    Inventors: Hisashi Yamada, Naoharu Yamada, Mirai Hara, Norihiro Katsumaru
  • Patent number: 8901656
    Abstract: Provided is a semiconductor wafer including a base wafer, a first insulating layer, and a semiconductor layer. Here, the base wafer, the first insulating layer and the semiconductor layer are arranged in an order of the base wafer, the first insulating layer and the semiconductor layer, the first insulating layer is made of an amorphous metal oxide or an amorphous metal nitride, the semiconductor layer includes a first crystal layer and a second crystal layer, the first crystal layer and the second crystal layer are arranged in an order of the first crystal layer and the second crystal layer in such a manner that the first crystal layer is positioned closer to the base wafer, and the electron affinity Ea1 of the first crystal layer is larger than the electron affinity Ea2 of the second crystal layer.
    Type: Grant
    Filed: August 30, 2013
    Date of Patent: December 2, 2014
    Assignees: Sumitomo Chemical Company, Limited, The University of Tokyo, National Institute of Advanced Industrial Science and Technology
    Inventors: Takeshi Aoki, Hisashi Yamada, Noboru Fukuhara, Masahiko Hata, Masafumi Yokoyama, SangHyeon Kim, Mitsuru Takenaka, Shinichi Takagi, Tetsuji Yasuda
  • Publication number: 20140291694
    Abstract: A nonpolar III-nitride film grown on a miscut angle of a substrate, in order to suppress the surface undulations, is provided. The surface morphology of the film is improved with a miscut angle towards an a-axis direction comprising a 0.15° or greater miscut angle towards the a-axis direction and a less than 30° miscut angle towards the a-axis direction.
    Type: Application
    Filed: June 16, 2014
    Publication date: October 2, 2014
    Applicant: THE REGENTS OF THE UNIVERSITY OF CALIFORNIA
    Inventors: Asako Hirai, Zhongyuan Jia, Makoto Saito, Hisashi Yamada, Kenji Iso, Steven P. DenBaars, Shuji Nakamura, James S. Speck
  • Patent number: 8791000
    Abstract: A nonpolar III-nitride film grown on a miscut angle of a substrate, in order to suppress the surface undulations, is provided. The surface morphology of the film is improved with a miscut angle towards an a-axis direction comprising a 0.15° or greater miscut angle towards the a-axis direction and a less than 30° miscut angle towards the a-axis direction.
    Type: Grant
    Filed: January 27, 2014
    Date of Patent: July 29, 2014
    Assignee: The Regents of the University of California
    Inventors: Asako Hirai, Zhongyuan Jia, Makoto Saito, Hisashi Yamada, Kenji Iso, Steven P. DenBaars, Shuji Nakamura, James S. Speck
  • Publication number: 20140203408
    Abstract: There is provided a method that includes forming a sacrificial layer and the semiconductor crystal layer on a semiconductor crystal layer formation wafer in the stated order, bonding together the semiconductor crystal layer formation wafer and a transfer-destination wafer such that a first surface of the semiconductor crystal layer and a second surface of the transfer-destination wafer face each other, and splitting the transfer-destination wafer from the semiconductor crystal layer formation wafer with the semiconductor crystal layer remaining on the transfer-destination wafer side, by etching away the sacrificial layer by immersing the semiconductor crystal layer formation wafer and the transfer-destination wafer wholly or partially in an etchant. Here, the transfer-destination wafer includes an inflexible wafer and an organic material layer, and a surface of the organic material layer is the second surface.
    Type: Application
    Filed: March 20, 2014
    Publication date: July 24, 2014
    Applicants: NATIONAL INSTITUTE OF ADVANCED INDUSTRIAL SCIENCE AND TECHNOLOGY, SUMITOMO CHEMICAL COMPANY, LIMITED
    Inventors: Tomoyuki TAKADA, Hisashi YAMADA, Masahiko HATA, Tatsuro MAEDA, Taro ITATANI, Tetsuji YASUDA
  • Patent number: 8779471
    Abstract: Provided is a field-effect transistor including a gate insulating layer, a first semiconductor crystal layer in contact with the gate insulating layer, and a second semiconductor crystal layer lattice-matching or pseudo lattice-matching the first semiconductor crystal layer. Here, the gate insulating layer, the first semiconductor crystal layer, and the second semiconductor crystal layer are arranged in the order of the gate insulating layer, the first semiconductor crystal layer, and the second semiconductor crystal layer, the first semiconductor crystal layer is made of Inx1Ga1-x1Asy1P1-y1 (0<x1?1, 0?y1?1), the second semiconductor crystal layer is made of Inx2Ga1-x2Asy2P1-y2 (0?x2?1, 0?y2?1, y2?y1), and the electron affinity Ea1 of the first semiconductor crystal layer is lower than the electron affinity Ea2 of the second semiconductor crystal layer.
    Type: Grant
    Filed: March 6, 2012
    Date of Patent: July 15, 2014
    Assignees: Sumitomo Chemical Company, Limited, The University of Tokyo, National Institute of Advanced Industrial Science and Technology
    Inventors: Masahiko Hata, Hisashi Yamada, Noboru Fukuhara, Shinichi Takagi, Mitsuru Takenaka, Masafumi Yokoyama, Tetsuji Yasuda, Yuji Urabe, Noriyuki Miyata, Taro Itatani, Hiroyuki Ishii