Patents by Inventor Hisashi Yamada

Hisashi Yamada has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250063857
    Abstract: This compound semiconductor substrate has a base layer having an in-plane lattice constant of a, a stress relaxation layer that relaxes strain that is received from the base layer and a functional layer having an in-plane lattice constant of b (a?b), the base layer, the stress relaxation layer and the functional layer are disposed in order of the base layer, the stress relaxation layer and the functional layer, in the functional layer, a region where a lattice is relaxed from a crystal lattice of the base layer is dominant, and the threading dislocation density of the functional layer is lower than 2.0×109 cm?2.
    Type: Application
    Filed: December 19, 2022
    Publication date: February 20, 2025
    Inventor: Hisashi YAMADA
  • Publication number: 20240416420
    Abstract: An additive manufacturing apparatus includes: a machining head; a beam nozzle through which a beam emitted from the machining head passes; a material feed unit that feeds a material to a workpiece; a first drive unit that moves a tip portion of the material relative to the workpiece; a second drive unit that moves the beam in a direction included in a reference plane perpendicular to a central axis of the beam nozzle; and a controller that determines, on the basis of a direction of travel, a direction of the movement of the beam, the direction of travel being included in the reference plane, the direction of travel being a direction in which the tip portion travels relative to the workpiece, and controls the first and second drive units such that the beam is movable in a manner different from movement of the tip portion relative to the workpiece.
    Type: Application
    Filed: June 21, 2022
    Publication date: December 19, 2024
    Applicant: Mitsubishi Electric Corporation
    Inventors: Daiji MORITA, Nobuyuki SUMI, Hisashi YAMADA
  • Publication number: 20240410077
    Abstract: Provided is a method and apparatus for producing a nitrogen compound through vapor phase growth using a gas supply module having a nozzle surface which faces a substrate, in which a plasma source gas containing a nitrogen element is converted into a plasma, the plasma is discharged toward the substrate from a plasma nozzle having an opening placed on the nozzle surface, a raw material gas is discharged from a raw material nozzle that opens around the outside of the plasma nozzle on the nozzle surface, and an active species containing nitrogen contained in the plasma is reacted with the raw material gas to form a nitrogen compound film on the substrate.
    Type: Application
    Filed: October 11, 2022
    Publication date: December 12, 2024
    Inventors: Xuelun WANG, Jaeho KIM, Naoto KUMAGAI, Hajime SAKAKITA, Hisashi YAMADA, Tetsuji SHIMIZU
  • Publication number: 20240254566
    Abstract: An analysis method may determine the presence of affection of at least any one of breast cancer, pancreatic cancer, lung cancer, gastric cancer, and colorectal cancer. The analysis method may include quantifying at least any one of hsa-miR-205-5p, hsa-miR-30e-5p, hsa-miR-106b-5p, hsa-miR-3613-5p, hsa-miR-483-5p, hsa-miR-574-3p, hsa-miR-125b-5p, hsa-miR-223-5p, hsa-miR-3613-3p, hsa-miR-941, hsa-miR-324-3p, hsa-miR-193a-5p, hsa-miR-4433a-3p, hsa-miR-29c-3p, hsa-miR-190a-5p, hsa-miR-885-5p, hsa-miR-194-5p, hsa-miR-29a-3p, hsa-miR-142-5p, hsa-miR-142-3p, hsa-miR-122-5p, hsa-miR-34a-5p, and hsa-miR-375-3p in a sample derived from an object.
    Type: Application
    Filed: February 29, 2024
    Publication date: August 1, 2024
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Takuya MIYAGAWA, Yoshitake SANO, Tomomi ANDO, Mitsuko ISHIHARA, Miho SAKO, Masaaki TAKADA, Hisashi YAMADA
  • Publication number: 20240062900
    Abstract: An information processing device according to an embodiment includes a hardware processor coupled to a memory. The hardware processor estimates morbidity representing a probability of a subject being suffering from a specific disease. The morbidity is estimated on the basis of: a first probability model representing a relation between a first physical quantity associated with the specific disease and a second physical quantity to be measured, a second probability model representing a relation between the first physical quantity and information about whether the subject is suffering from the specific disease, a prior probability of morbidity representing a probability of the subject being suffering from the specific disease in a situation where no information has been obtained with respect to the first physical quantity or the second physical quantity related to the subject, and the second physical quantity obtained by measuring the subject.
    Type: Application
    Filed: February 24, 2023
    Publication date: February 22, 2024
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Masaaki TAKADA, Miho SAKO, Hisashi YAMADA
  • Publication number: 20220398358
    Abstract: According to an embodiment, an information processing device includes one or more processors. The one or more processors are configured to: build a prediction model for predicting prediction data for a second region included in a plurality of regions based on acquired data acquired for one or more first regions included in the plurality of regions; and predict the prediction data based on the acquired data by using the prediction model.
    Type: Application
    Filed: February 25, 2022
    Publication date: December 15, 2022
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Lele XI, Arika FUKUSHIMA, Hisashi YAMADA
  • Publication number: 20220343215
    Abstract: An information processing apparatus according to one embodiment includes one or more hardware processors coupled to a memory. The hardware processors function as an acquisition unit, a model generation unit, and a model generation unit. The acquisition unit serves to acquire one or more patterns from among multiple patterns each representing temporal variation of first data being data to be predicted. The patterns are determined for a first region designated out of regions serving as prediction targets of the first data. The model generation unit serves to generate a prediction model for predicting the temporal variation of the first data in the first region. The prediction model is generated on the basis of the acquired patterns. The model generation unit serves to determine a parameter of the prediction model.
    Type: Application
    Filed: February 25, 2022
    Publication date: October 27, 2022
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Arika FUKUSHIMA, Lele XI, Hisashi YAMADA
  • Patent number: 10763332
    Abstract: Provided is a semiconductor wafer in which a nitride crystal layer on a silicon wafer includes a reaction suppressing layer to suppress reaction between a silicon atom and a Group-III atom, a stress generating layer to generate compressive stress and an active layer in which an electronic element is to be formed, the reaction suppressing layer, the stress generating layer and the active layer are arranged in an order of the reaction suppressing layer, the stress generating layer and the active layer with the reaction suppressing layer being positioned the closest to the silicon wafer, and the stress generating layer includes a first crystal layer having a bulk crystal lattice constant of al and a second crystal layer in contact with a surface of the first crystal layer that faces the active layer, where the second crystal layer has a bulk crystal lattice constant of a2 (a1<a2).
    Type: Grant
    Filed: May 4, 2017
    Date of Patent: September 1, 2020
    Assignee: SUMITOMO CHEMICAL COMPANY, LIMITED
    Inventors: Hisashi Yamada, Taiki Yamamoto, Kenji Kasahara
  • Patent number: 9828695
    Abstract: A nonpolar III-nitride film grown on a miscut angle of a substrate, in order to suppress the surface undulations, is provided. The surface morphology of the film is improved with a miscut angle towards an a-axis direction comprising a 0.15° or greater miscut angle towards the a-axis direction and a less than 30° miscut angle towards the a-axis direction.
    Type: Grant
    Filed: April 20, 2016
    Date of Patent: November 28, 2017
    Assignee: THE REGENTS OF THE UNIVERSITY OF CALIFORNIA
    Inventors: Asako Hirai, Zhongyuan Jia, Makoto Saito, Hisashi Yamada, Kenji Iso, Steven P. DenBaars, Shuji Nakamura, James S. Speck
  • Publication number: 20170327969
    Abstract: A nonpolar III-nitride film grown on a miscut angle of a substrate. The miscut angle towards the <000-1> direction is 0.75° or greater miscut and less than 27° miscut towards the <000-1> direction. Surface undulations are suppressed and may comprise faceted pyramids. A device fabricated using the film is also disclosed. A nonpolar III-nitride film having a smooth surface morphology fabricated using a method comprising selecting a miscut angle of a substrate upon which the nonpolar III-nitride films are grown in order to suppress surface undulations of the nonpolar III-nitride films. A nonpolar III-nitride-based device grown on a film having a smooth surface morphology grown on a miscut angle of a substrate which the nonpolar III-nitride films are grown. The miscut angle may also be selected to achieve long wavelength light emission from the nonpolar film.
    Type: Application
    Filed: May 26, 2017
    Publication date: November 16, 2017
    Applicant: The Regents of the University of California
    Inventors: Kenji Iso, Hisashi Yamada, Makoto Saito, Asako Hirai, Steven P. DenBaars, James S. Speck, Shuji Nakamura
  • Publication number: 20170236906
    Abstract: Provided is a semiconductor wafer in which a nitride crystal layer on a silicon wafer includes a reaction suppressing layer to suppress reaction between a silicon atom and a Group-III atom, a stress generating layer to generate compressive stress and an active layer in which an electronic element is to be formed, the reaction suppressing layer, the stress generating layer and the active layer are arranged in an order of the reaction suppressing layer, the stress generating layer and the active layer with the reaction suppressing layer being positioned the closest to the silicon wafer, and the stress generating layer includes a first crystal layer having a bulk crystal lattice constant of al and a second crystal layer in contact with a surface of the first crystal layer that faces the active layer, where the second crystal layer has a bulk crystal lattice constant of a2 (a1<a2).
    Type: Application
    Filed: May 4, 2017
    Publication date: August 17, 2017
    Applicant: SUMITOMO CHEMICAL COMPANY, LIMITED
    Inventors: Hisashi YAMADA, Taiki YAMAMOTO, Kenji KASAHARA
  • Publication number: 20160230312
    Abstract: A nonpolar III-nitride film grown on a miscut angle of a substrate, in order to suppress the surface undulations, is provided. The surface morphology of the film is improved with a miscut angle towards an ?-axis direction comprising a 0.15° or greater miscut angle towards the ?-axis direction and a less than 30° miscut angle towards the ?-axis direction.
    Type: Application
    Filed: April 20, 2016
    Publication date: August 11, 2016
    Applicant: THE REGENTS OF THE UNIVERSITY OF CALIFORNIA
    Inventors: Asako Hirai, Zhongyuan Jia, Makoto Saito, Hisashi Yamada, Kenji Iso, Steven P. DenBaars, Shuji Nakamura, James S. Speck
  • Patent number: 9340899
    Abstract: A nonpolar III-nitride film grown on a miscut angle of a substrate, in order to suppress the surface undulations, is provided. The surface morphology of the film is improved with a miscut angle towards an a-axis direction comprising a 0.15° or greater miscut angle towards the a-axis direction and a less than 30° miscut angle towards the a-axis direction.
    Type: Grant
    Filed: June 16, 2014
    Date of Patent: May 17, 2016
    Assignee: The Regents of the University of California
    Inventors: Asako Hirai, Zhongyuan Jia, Makoto Saito, Hisashi Yamada, Kenji Iso, Steven P. DenBaars, Shuji Nakamura, James S. Speck
  • Patent number: 9112035
    Abstract: A semiconductor substrate includes a substrate, an insulating layer, and a semiconductor layer. The insulating layer is over and in contact with the substrate. The insulating layer includes at least one of an amorphous metal oxide and an amorphous metal nitride. The semiconductor layer is over and in contact with the insulating layer. The semiconductor layer is formed by crystal growth.
    Type: Grant
    Filed: March 2, 2012
    Date of Patent: August 18, 2015
    Assignees: SUMITOMO CHEMICAL COMPANY, LIMITED, THE UNIVERSITY OF TOKYO, NATIONAL INSTITUTE OF ADVANCED INDUSTRIAL SCIENCE AND TECHNOLOGY
    Inventors: Hisashi Yamada, Masahiko Hata, Masafumi Yokoyama, Mitsuru Takenaka, Shinichi Takagi, Tetsuji Yasuda, Hideki Takagi, Yuji Urabe
  • Publication number: 20150199382
    Abstract: A related content retrieval device that can retrieve a wide variety of related contents. The related content retrieval device includes: an input unit for implementing input of a content; a metadata acquisition unit for acquiring metadata of the content input by the input unit; a posted text acquisition unit for acquiring a posted text related to the metadata acquired by the metadata acquisition unit, from a posting server accumulating user posted texts; a related content acquisition unit for acquiring a related content related to the posted text acquired by the posted text acquisition unit, from a retrieval server capable of retrieving a content on a network device; and an output unit for outputting the related content acquired by the related content acquisition unit.
    Type: Application
    Filed: May 8, 2013
    Publication date: July 16, 2015
    Applicant: NTT DOCOMO, INC.
    Inventors: Hisashi Yamada, Naoharu Yamada, Mirai Hara, Norihiro Katsumaru
  • Patent number: 8901656
    Abstract: Provided is a semiconductor wafer including a base wafer, a first insulating layer, and a semiconductor layer. Here, the base wafer, the first insulating layer and the semiconductor layer are arranged in an order of the base wafer, the first insulating layer and the semiconductor layer, the first insulating layer is made of an amorphous metal oxide or an amorphous metal nitride, the semiconductor layer includes a first crystal layer and a second crystal layer, the first crystal layer and the second crystal layer are arranged in an order of the first crystal layer and the second crystal layer in such a manner that the first crystal layer is positioned closer to the base wafer, and the electron affinity Ea1 of the first crystal layer is larger than the electron affinity Ea2 of the second crystal layer.
    Type: Grant
    Filed: August 30, 2013
    Date of Patent: December 2, 2014
    Assignees: Sumitomo Chemical Company, Limited, The University of Tokyo, National Institute of Advanced Industrial Science and Technology
    Inventors: Takeshi Aoki, Hisashi Yamada, Noboru Fukuhara, Masahiko Hata, Masafumi Yokoyama, SangHyeon Kim, Mitsuru Takenaka, Shinichi Takagi, Tetsuji Yasuda
  • Publication number: 20140291694
    Abstract: A nonpolar III-nitride film grown on a miscut angle of a substrate, in order to suppress the surface undulations, is provided. The surface morphology of the film is improved with a miscut angle towards an a-axis direction comprising a 0.15° or greater miscut angle towards the a-axis direction and a less than 30° miscut angle towards the a-axis direction.
    Type: Application
    Filed: June 16, 2014
    Publication date: October 2, 2014
    Applicant: THE REGENTS OF THE UNIVERSITY OF CALIFORNIA
    Inventors: Asako Hirai, Zhongyuan Jia, Makoto Saito, Hisashi Yamada, Kenji Iso, Steven P. DenBaars, Shuji Nakamura, James S. Speck
  • Patent number: 8791000
    Abstract: A nonpolar III-nitride film grown on a miscut angle of a substrate, in order to suppress the surface undulations, is provided. The surface morphology of the film is improved with a miscut angle towards an a-axis direction comprising a 0.15° or greater miscut angle towards the a-axis direction and a less than 30° miscut angle towards the a-axis direction.
    Type: Grant
    Filed: January 27, 2014
    Date of Patent: July 29, 2014
    Assignee: The Regents of the University of California
    Inventors: Asako Hirai, Zhongyuan Jia, Makoto Saito, Hisashi Yamada, Kenji Iso, Steven P. DenBaars, Shuji Nakamura, James S. Speck
  • Publication number: 20140203408
    Abstract: There is provided a method that includes forming a sacrificial layer and the semiconductor crystal layer on a semiconductor crystal layer formation wafer in the stated order, bonding together the semiconductor crystal layer formation wafer and a transfer-destination wafer such that a first surface of the semiconductor crystal layer and a second surface of the transfer-destination wafer face each other, and splitting the transfer-destination wafer from the semiconductor crystal layer formation wafer with the semiconductor crystal layer remaining on the transfer-destination wafer side, by etching away the sacrificial layer by immersing the semiconductor crystal layer formation wafer and the transfer-destination wafer wholly or partially in an etchant. Here, the transfer-destination wafer includes an inflexible wafer and an organic material layer, and a surface of the organic material layer is the second surface.
    Type: Application
    Filed: March 20, 2014
    Publication date: July 24, 2014
    Applicants: NATIONAL INSTITUTE OF ADVANCED INDUSTRIAL SCIENCE AND TECHNOLOGY, SUMITOMO CHEMICAL COMPANY, LIMITED
    Inventors: Tomoyuki TAKADA, Hisashi YAMADA, Masahiko HATA, Tatsuro MAEDA, Taro ITATANI, Tetsuji YASUDA
  • Patent number: 8779471
    Abstract: Provided is a field-effect transistor including a gate insulating layer, a first semiconductor crystal layer in contact with the gate insulating layer, and a second semiconductor crystal layer lattice-matching or pseudo lattice-matching the first semiconductor crystal layer. Here, the gate insulating layer, the first semiconductor crystal layer, and the second semiconductor crystal layer are arranged in the order of the gate insulating layer, the first semiconductor crystal layer, and the second semiconductor crystal layer, the first semiconductor crystal layer is made of Inx1Ga1-x1Asy1P1-y1 (0<x1?1, 0?y1?1), the second semiconductor crystal layer is made of Inx2Ga1-x2Asy2P1-y2 (0?x2?1, 0?y2?1, y2?y1), and the electron affinity Ea1 of the first semiconductor crystal layer is lower than the electron affinity Ea2 of the second semiconductor crystal layer.
    Type: Grant
    Filed: March 6, 2012
    Date of Patent: July 15, 2014
    Assignees: Sumitomo Chemical Company, Limited, The University of Tokyo, National Institute of Advanced Industrial Science and Technology
    Inventors: Masahiko Hata, Hisashi Yamada, Noboru Fukuhara, Shinichi Takagi, Mitsuru Takenaka, Masafumi Yokoyama, Tetsuji Yasuda, Yuji Urabe, Noriyuki Miyata, Taro Itatani, Hiroyuki Ishii