Abstract: A clock signal initialization circuit capable of preventing the operating frequency of a semiconductor integrated circuit from exceeding the maximum permissible frequency determined based on the power consumption of that semiconductor integrated circuit even when the PLL circuit is in a transient state at the start-up is provided. A clock signal initialization circuit for a semiconductor integrated circuit that operates in synchronization with a clock signal generated by a PLL circuit, includes a controller that derives a clock signal having a frequency no greater than a maximum permissible frequency determined based on a power consumption of the semiconductor integrated circuit as a supply clock signal to the semiconductor integrated circuit at least until the PLL circuit becomes a locked state after power-on.

Abstract: A clock signal initialization circuit capable of preventing the operating frequency of a semiconductor integrated circuit from exceeding the maximum permissible frequency determined based on the power consumption of that semiconductor integrated circuit even when the PLL circuit is in a transient state at the start-up is provided. A clock signal initialization circuit for a semiconductor integrated circuit that operates in synchronization with a clock signal generated by a PLL circuit, includes a controller that derives a clock signal having a frequency no greater than a maximum permissible frequency determined based on a power consumption of the semiconductor integrated circuit as a supply clock signal to the semiconductor integrated circuit at least until the PLL circuit becomes a locked state after power-on.

Abstract: A characteristic adjustment circuit for a logic circuit includes an oscillator that includes a first metal-oxide semiconductor (MOS) transistor and outputs an oscillation output, and a voltage generator that generates a voltage of a second MOS transistor of the logic circuit according to a phase difference between the oscillation output and a reference signal.