Abstract: To provide a floating point arithmetic circuit for efficiently defecting an error, which has a large numerical error, with a less circuit amount, the floating point arithmetic circuit comprises a first arithmetic unit for outputting a first arithmetic result, a second arithmetic unit for outputting a second arithmetic result, and a comparison circuit for making a comparison between the first and the second arithmetic results by a predetermined bit width.

Abstract: An information-processing device that executes a specific process more frequently than other processes among a variety of processes is provided. The information-processing device includes a first processor capable of executing an instruction set corresponding to the variety of processes, and a second processor capable of executing a portion of or the entire instruction set, the second processor being capable of executing a part of the instruction set corresponding to the specific process more efficiently than the first processor, wherein the second processor executes the specific process whereas the first processor executes the other processes. Accordingly, the information-processing device can execute a variety of instructions efficiently.

Abstract: To provide a floating point arithmetic circuit for efficiently defecting an error, which has a large numerical error, with a less circuit amount, the floating point arithmetic circuit comprises a first arithmetic unit for outputting a first arithmetic result, a second arithmetic unit for outputting a second arithmetic result, and a comparison circuit for making a comparison between the first and the second arithmetic results by a predetermined bit width.

Abstract: The present invention relates to a voltage stabilizer that stabilizes the voltage of a power supply line on a semiconductor substrate and is intended to provide a voltage stabilizer having a small mounting area on the semiconductor substrate, capable of stabilizing the voltage of the power supply path connecting the power supply and semiconductor substrate. The voltage stabilizer includes a monitoring section 110 connected to the power supply line Vdd that monitors the potential of the power supply line Vdd and outputs a monitor signal indicating the monitoring result and a first current control section 120 that passes a current from the power supply line Vdd according to the monitor signal to stabilize the voltage of the power supply line Vdd, capable of freely passing a current continuously.

Abstract: The present invention relates to a voltage stabilizer that stabilizes the voltage of a power supply line on a semiconductor substrate and is intended to provide a voltage stabilizer having a small mounting area on the semiconductor substrate, capable of stabilizing the voltage of the power supply path connecting the power supply and semiconductor substrate. The voltage stabilizer includes a monitoring section 110 connected to the power supply line Vdd that monitors the potential of the power supply line Vdd and outputs a monitor signal indicating the monitoring result and a first current control section 120 that passes a current from the power supply line Vdd according to the monitor signal to stabilize the voltage of the power supply line Vdd, capable of freely passing a current continuously.

Abstract: Disclosed is a computer in which an error caused by an intermittent failure is corrected by using a misprediction recovery mechanism which performs recovery processing if, after having predicted a branch destination of a branch instruction and speculatively executed an instruction at the predicted branch destination, it turns out that the branch prediction was wrong. The computer includes an error detection mechanism for detecting an error in logic operation of the computer, and an instruction re-execution mechanism for correcting an error caused by an intermittent failure when an error is detected by the error detection mechanism, by restoring the computer, using the misprediction recovery mechanism, to a state that existed before the occurrence of the error, and by re-executing a sequence of instructions including the instruction where the error is detected.

Abstract: An information-processing device that executes a specific process more frequently than other processes among a variety of processes is provided. The information-processing device includes a first processor capable of executing an instruction set corresponding to the variety of processes, and a second processor capable of executing a portion of or the entire instruction set, the second processor being capable of executing a part of the instruction set corresponding to the specific process more efficiently than the first processor, wherein the second processor executes the specific process whereas the first processor executes the other processes. Accordingly, the information-processing device can execute a variety of instructions efficiently.

Abstract: Integrated circuit formed from a semiconductor body having a rectangular grid pattern formed on the body. The grid pattern is defined by lines extending at right angles to each other along X and Y axes. A plurality of basic cells are provided which have a plurality of active elements therein. Each of the basic cells is selected from a limited number of basic cells of different designs. Each of the basic cells is disposed within a rectangular area no greater than a predetermined size and overlying a plurality of grid lines on both the X and Y axes so that each basic cell overlies a plurality of intersections of the grid lines which define predetermined grid points. Each basic cell includes a power bus, a ground bus, input leads and an output having a predetermined arrangement with respect to certain grid points. The power bus and ground bus and the input leads and output of each basic cell are connected to the basic cell.

Abstract: Integrated circuit formed from a semiconductor body having a rectangular grid pattern formed on the body. The grid pattern is defined by lines extending at right angles to each other along X and Y axes. A plurality of basic cells are provided which have a plurality of active elements therein. Each of the basic cells is selected from a limited number of basic cells of different designs. Each of the basic cells is disposed within a rectangular area no greater than a predetermined size and overlying a plurality of grid lines on both the X and Y axes so that each basic cell overlies a plurlity of intersections of the grid lines which define predetermined grid points. Each basic cell includes a power bus, a ground bus, input leads and an output having a predetermined arrangement with respect to certain grid points. The power bus and ground bus and the input leads and output of each basic cell are connected to the basic cell.

Abstract: A multi-plane video RAM for displaying a color image on a display apparatus. A multi-plane bit operation unit is used for calculating input data from an external stage based on a predetermined rule corresponding to an information applied from the external stage. Memory arrays are operatively connected to the multi-plane bit operation unit for writing resultant data calculated by the multi-plane bit operation unit. Each array having three-dimensionally arranged k sets of memory planes each consisting of m (rows).times.n (columns); wherein the same corresponding positions of the k sets of memory planes are simultaneously accessed and the resultant data calculated by the multi-plane bit operation unit are also simultaneously written thereto.

Abstract: A vector pattern processing circuit for a bit map display system including a display unit having a plurality of quasi regions in a matrix form defined in a plane of the display unit each forming N.times.N dots. The circuit includes first and second memory units each including a plurality of words formed in a matrix, each word having an N.times.N bits structure; the words in the first memory unit corresponding to diagonal quasi regions of the display unit and the words in the second memory unit corresponding other diagonal quasi regions; first and second word register units, each having an N.times.N bits structure; a digital differential analyzer (DDA) generating a first dot data of a primary axis for a processing vector pattern and a second dot data of a subsidiary axis perpendicular to the primary axis in response to a gradient of the vector pattern along the primary axis for every N dots in the primary axis.

Abstract: A clocked memory comprising a memory matrix having a plurality of memory cells arranged in rows and columns on a semiconductor substrate; a plurality of word select lines in said memory matrix, a plurality of bit lines crossing said select lines and connecting to said memory cells in each column; a drive circuit for driving said word select lines; a plurality of presence amplifiers connected to said bit lines; and a sense clock line parallel to said word select lines and connected to a gate of a transistor in said presence amplifier; and a presense drive circuit connected to said sense clock line and operated by a clock signal, said presense drive circuit having a transistor with controlled charging capability so as to conduct said transistor responsive to the charge of the memory cell in said each column.

Abstract: A majority decision logic circuit has an odd number of elementary input signal circuits connected in parallel with a power source, each of the elementary input signal circuits being composed of a pair of P- and N-channel MOS transistors, the drains of the MOS transistors being interconnected to form an output terminal at the connection point and the gates being interconnected to form an input terminal at the connection point, all the output terminals of the elementary input signal circuits being connected together to form the output terminal of the majority decision logic circuit. A majority decision logic circuit has, in addition to the odd number of elementary input signal circuits, a plurality of logic circuits having their output terminals respectively connected to the input terminal of the elementary input signal circuits.

Abstract: An error correcting circuit utilizing a cube circuit for correcting errors in data having n+1 bits in accordance with the syndromes S.sub.1 and S.sub.3 from a check matrix H. The circuit comprises a generator for generating syndromes S.sub.1 and S.sub.3, means for providing (S.sub.1 -a.sub.i) based on the modulo 2 calculation for the i.sub.th line vector ##EQU1## OF THE CHECK MATRIX H corresponding to each data bit d.sub.1, means for multiplying (S.sub.1 -a.sub.i) three times, check means for checking the coincidence between (S.sub.1 -a.sub.i) and (S.sub.3 -a.sub.i.sup.3), and an inverting means for inverting the d.sub.i bit when the coincidence is detected.In the present invention, by utilizing a cube circuit the check circuit can be simplified.