Patents by Inventor Hisashige Nishida

Hisashige Nishida has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6979905
    Abstract: In a semiconductor device in which a semiconductor chip is stacked on a substrate, an interposer chip having wirings is provided under the semiconductor chip. A bonding pad of the semiconductor chip is electrically connected to a bonding terminal provided on the substrate via the interposer chip by wire bonding. The interposer chip prevents a semiconductor element formed in the semiconductor chip from deteriorating in terms of an electric property and from being physically damaged. Further, the wire bonding strength does not drop. Moreover, it is possible to form a fine wiring pitch for relaying a wire-bonding wire.
    Type: Grant
    Filed: January 23, 2004
    Date of Patent: December 27, 2005
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Hisashige Nishida, Yoshiki Sota, Hiroyuki Juso
  • Publication number: 20040150084
    Abstract: In a semiconductor device in which a semiconductor chip is stacked on a substrate, an interposer chip having wirings is provided under the semiconductor chip. A bonding pad of the semiconductor chip is electrically connected to a bonding terminal provided on the substrate via the interposer chip by wire bonding. The interposer chip prevents a semiconductor element formed in the semiconductor chip from deteriorating in terms of an electric property and from being physically damaged. Further, the wire bonding strength does not drop. Moreover, it is possible to form a fine wiring pitch for relaying a wire-bonding wire.
    Type: Application
    Filed: January 23, 2004
    Publication date: August 5, 2004
    Applicant: SHARP KABUSHIKI KAISHA
    Inventors: Hisashige Nishida, Yoshiki Sota, Hiroyuki Juso
  • Patent number: 6734557
    Abstract: A semiconductor device comprising: a substrate; first and second interconnection patterns respectively provided on upper and lower surfaces of the substrate; a through-hole electrode extending through the substrate for electrically connecting the first and second interconnection patterns; a semiconductor chip provided on the upper surface of the substrate and electrically connected to the first interconnection pattern; and a resist film covering the second interconnection pattern; the second interconnection pattern comprising a generally round land and a lead interconnection portion extending from the land, the resist film having an opening formed therein for exposing the entire land, the opening having a curved edge surrounding a peripheral edge of the land and a linear edge linearly extending along a boundary between the land and the lead interconnection portion, the exposed land having a solder ball as an external terminal thereon.
    Type: Grant
    Filed: February 21, 2003
    Date of Patent: May 11, 2004
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Kiyomi Taniguchi, Hisashige Nishida
  • Publication number: 20030173666
    Abstract: A semiconductor device comprising: a substrate; first and second interconnection patterns respectively provided on upper and lower surfaces of the substrate; a through-hole electrode extending through the substrate for electrically connecting the first and second interconnection patterns; a semiconductor chip provided on the upper surface of the substrate and electrically connected to the first interconnection pattern; and a resist film covering the second interconnection pattern; the second interconnection pattern comprising a generally round land and a lead interconnection portion extending from the land, the resist film having an opening formed therein for exposing the entire land, the opening having a curved edge surrounding a peripheral edge of the land and a linear edge linearly extending along a boundary between the land and the lead interconnection portion, the exposed land having a solder ball as an external terminal thereon.
    Type: Application
    Filed: February 21, 2003
    Publication date: September 18, 2003
    Inventors: Kiyomi Taniguchi, Hisashige Nishida
  • Patent number: RE41826
    Abstract: In a semiconductor device in which a semiconductor chip is stacked on a substrate, an interposer chip having wirings is provided under the semiconductor chip. A bonding pad of the semiconductor chip is electrically connected to a bonding terminal provided on the substrate via the interposer chip by wire bonding. The interposer chip prevents a semiconductor element formed in the semiconductor chip from deteriorating in terms of an electric property and from being physically damaged. Further, the wire bonding strength does not drop. Moreover, it is possible to form a fine wiring pitch for relaying a wire-bonding wire.
    Type: Grant
    Filed: June 11, 2007
    Date of Patent: October 19, 2010
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Hisashige Nishida, Yoshiki Sota, Hiroyuki Juso