Abstract: A pulse stretching circuit having a pulse delay circuit for receiving an input pulse signal and for outputting a delay pulse signal, and a pulse adjustment circuit, connected to the pulse delay circuit, receiving the input pulse signal and the delay pulse signal and for outputting an output pulse signal having a pulse width longer than a pulse width of the input pulse signal. The pulse adjustment circuit causes a leading edge of the output pulse signal in response to a leading edge of the input pulse signal, keeps a state in which the output pulse signal is displaced with the leading edge thus caused longer than a total time of times for both pulse widths of the input pulse signal and the delay pulse signal, and causes a trailing edge of the output pulse signal in response to a trailing edge of the delay pulse signal.

Abstract: A pulse stretching circuit having a pulse delay circuit for receiving an input pulse signal and for outputting a delay pulse signal, and a pulse adjustment circuit, connected to the pulse delay circuit, receiving the input pulse signal and the delay pulse signal and for outputting an output pulse signal having a pulse width longer than a pulse width of the input pulse signal. The pulse adjustment circuit causes a leading edge of the output pulse signal in response to a leading edge of the input pulse signal, keeps a state in which the output pulse signal is displaced with the leading edge thus caused longer than a total time of times for both pulse widths of the input pulse signal and the delay pulse signal, and causes a trailing edge of the output pulse signal in response to a trailing edge of the delay pulse signal.

Abstract: A pulse stretching circuit having a pulse delay circuit for receiving an input pulse signal and for outputting a delay pulse signal, and a pulse adjustment circuit, connected to the pulse delay circuit, receiving the input pulse signal and the delay pulse signal and for outputting an output pulse signal having a pulse width longer than a pulse width of the input pulse signal. The pulse adjustment circuit causes a leading edge of the output pulse signal in response to a leading edge of the input pulse signal, keeps a state in which the output pulse signal is displaced with the leading edge thus caused longer than a total time of times for both pulse widths of the input pulse signal and the delay pulse signal, and causes a trailing edge of the output pulse signal in response to a trailing edge of the delay pulse signal.

Abstract: The pulse width adjusting circuit includes a pulse delaying circuit for inputting an inputted pulse signal a and for outputting a plurality of different delayed pulse signals b1, b2, . . . , a transmission gate for inputting an inputted pulse signal a and controlling the passage of the inputted pulse signal a in response to the application of two delayed pulse signals from among the plurality of different delayed pulse signals b1, b2, . . . , and a pulse width setting circuit connected to the transmission gate for setting the pulse width of an outputted pulse signal c generated on the basis of the inputted pulse signal a passing through the transmission gate.

Abstract: A parallel CAM that can perform a parity check fast at the search time. The CAM searches all addresses at the same time and determines whether or not the same data as input data is stored. The CAM includes a write search parity generator for generating parities of n-bit write and search data, a plurality of memory locations corresponding to a plurality of addresses, and a NAND circuit for activating a parity error signal if at least one of valid parity match signals outputted from the memory locations is inactive. Each memory location includes n data memory cells, a parity memory cell, an exclusive OR circuit for judging whether or not the parities match, and activating a parity match signal, if they are matched, and a NAND circuit for validating the parity match signal using a data match signal.

Abstract: An asynchronous pseudo SRAM having compatibility with asynchronous SRAMs. A read request or a write request of data is provided at arbitrary timing to the asynchronous pseudo SRAM, the asynchronous pseudo SRAM includes a memory cell array comprising dynamic memory cells; an array control circuit that is activated in response to an access enable signal, the array control circuit reads data from or writes data in the memory cell array in response to address signals, and the array control circuit activates a busy signal during reading or writing of data; an access reception circuit for receiving the read request or the write request to activate an access wait signal and inactivating the access wait signal in response to the access enable signal; and an access activation circuit for activating the access enable signal in response to activation of the access wait signal and inactivation of the busy signal.

Abstract: A sense-amplifying circuit amplifies a voltage difference between a first signal source and a second signal source. A first inverter has a first intermediate node from which a first output extends. A second inverter has a second intermediate node from which a second output extends. The second inverter is recursively cross-coupled with the first inverter. A first power source switch connects the first and second inverters to a first power source line. A second power source switch connects the first and the second inverters to a second power source line. A first sense-amplifying switch connects the first signal source to the first intermediate node. A second sense-amplifying switch connects the second signal source to the second intermediate node. A first pre-charge switch connects the first intermediate node to the second power source line. A second pre-charge switch connects the second intermediate node to the second power source line.

Abstract: A memory including at least one memory cell array and an access control circuit for controlling access to the memory array. The access control circuit includes an access command circuit (ADRCTL) that receives a first (CE) and a second (ADV) input signals and outputs an access command signal (ACMDS) enabling commencement of memory access, and a command discriminating circuit (CMDDEC) that receives the first (CE) and second (ADV) input signals, a third (OE) and a fourth (WE) input signals, and a clock signal (CLK), and that outputs a command discriminating signal (WRITE) for specifying whether the access command signal is for a read operation or a write operation.

Abstract: A non-volatile memory device according to one embodiment comprises a plurality of memory cells each comprising a magneto resistive element and a selection transistor; wherein at least some of the memory cells are arranged into a two dimensional array; a first interconnect line extending in a first direction of the memory array and functioning as a gate electrode of a selection transistor included in each memory cell; a second interconnect line extending in the first direction of the memory array; a third interconnect line extending in a second direction; wherein the magneto resistive element of at least some of the memory cells is sandwiched between the second and third interconnect lines, wherein the second interconnect line extends at least partially along all magneto resistive elements in a particular one of the memory cells.

Abstract: In the case of magnetic head of magnetoresistance effect type whose breakdown voltage is as low as 0.3 V, it is impractical to ignore even a very small amount of static electricity that occurs during fabrication or use. In one embodiment, the desired magnetic head is produced by forming an SiO2 layer on a silicon slider, thereby forming an SOI substrate; forming on the SOI substrate circuits to protect a TMR element from overvoltage and a read-write circuit; forming field effect transistors from an Si semiconductor layer (formed by reduction of the SiO2 layer or epitaxial growth on the SiO2 layer); forming three electrodes (source, gate, drain) on the Si semiconductor layer; forming a Schottky diode by Schottky contact (metal) with the Si semiconductor layer; forming overvoltage protective circuits of aluminum wiring on the SOI substrate; and forming a TMR element.

Abstract: A differential current-sensing amplifier includes two inverters, two resistors, a NOR gate, and five switches. The first inverter has a first output; the second inverter has a second output. The first resistor is connected between the first inverter and ground; the second resistor is connected between the second inverter and ground. A current to be sensed is input between the first resistor and the first inverter; a reference current is input between the second resistor and the second inverter. The first switch is connected between the first output and ground, the second switch is connected between the second output and ground, and the third switch is connected between the first and the second inverters and power. The first and the second switches are turned off, and the third switch is turned on, to compare the current to be sensed in relation to the reference current.

Abstract: A magnetic random access memory (MRAM) array is disclosed herein in which a plurality of wordlines and a plurality of bitlines are provided in matrix form, the wordlines including read wordlines and write wordlines, and memory elements are provided at the intersections of the wordlines and the bitlines, memory elements, respectively, including at least a ferromagnetic layer having a magnetization direction determined by the orientation of a magnetic field generated by an electric current passing through the bitline, and a read wordline driver connected to the memory array adapted to provide a first read signal to a first read wordline of a plurality of read wordlines, wherein a second read signal is provided to activate a second read wordline while the first read wordline remains activated.

Abstract: The present invention is a PSRAM in which a burst length can be increased without increasing consumed current, and a burst operation method therefor. In operation, column selection lines CSL1 and CSL2 are driven in order during activation of sense amplifiers. This causes bit switches BSW1-BSW8 to be turned on in units of four bit switches and then 8-bit read data RD is latched from bit line pairs BL1-BL8 into prefetch/preload latches PFPLL1-PFPLL8 in units of 4-bits. The 8-bit read data RD is continuously output to a single data I/O bus I/O1 in units of one bit and in order.

Abstract: A Magnetic Random Access Memory (MRAM), in which very little current flows through MTJ elements and very little voltage is applied across them, the MRAM being provided with sense-amplifiers capable of amplifying the potential difference between their corresponding pairs of bit lines at high speed. This is accomplished by a sense amplifier including CMOS inverters cross-connected or connected in loop, a P-channel MOS transistor for shutting the power off during standby, and N-channel MOS transistors for initializing the output of the sense amplifier during standby. A ground terminal of the inverter is connected to a bit line through a transistor of a bit switch, and a ground terminal of the inverter is connected to a bit line through a transistor of a bit switch.

Abstract: A differential current-sensing amplifier includes two inverters, two resistors, and three switches. The first inverter has a first output and the second inverter has a second output. The first resistor is connected between the first inverter and ground, and the second resistor is connected between the second inverter and ground. A current to be sensed is input between the first resistor and the first inverter, and a reference current is input between the second resistor and the second inverter. The first switch is connected between the first output and ground, the second switch is connected between the second output and ground, and the third switch is connected between the first and the second inverters and power. The first and the second switches are turned off, and the third switch is turned on, to compare the current to be sensed in relation to the reference current.

Abstract: A non-volatile memory device according to one embodiment comprises a plurality of memory cells each comprising a magneto resistive element and a selection transistor; wherein at least some of the memory cells are arranged into a two dimensional array; a first interconnect line extending in a first direction of the memory array and functioning as a gate electrode of a selection transistor included in each memory cell; a second interconnect line extending in the first direction of the memory array; a third interconnect line extending in a second direction; wherein the magneto resistive element of at least some of the memory cells is sandwiched between the second and third interconnect lines, wherein the second interconnect line extends at least partially along all magneto resistive elements in a particular one of the memory cells.

Abstract: A non-volatile memory device according to one embodiment includes a plurality of memory cells each comprising a magneto resistive element and a selection transistor, where the memory cells are arranged into a two dimensional array. A first interconnect line extends in a first direction of the memory array and functions as a gate electrode of a selection transistor included in each memory cell. A second interconnect line extends in the first direction of the memory array. A third interconnect line extends in a second direction. The magneto resistive element of at least some of the memory cells is sandwiched between the second and third interconnect lines.

Abstract: An asynchronous pseudo SRAM having compatibility with asynchronous SRAMs. A read request or a write request of data is provided at arbitrary timing to the asynchronous pseudo SRAM, the asynchronous pseudo SRAM includes a memory cell array comprising dynamic memory cells; an array control circuit that is activated in response to an access enable signal, the array control circuit reads data from or writes data in the memory cell array in response to address signals, and the array control circuit activates a busy signal during reading or writing of data; an access reception circuit for receiving the read request or the write request to activate an access wait signal and inactivating the access wait signal in response to the access enable signal; and an access activation circuit for activating the access enable signal in response to activation of the access wait signal and inactivation of the busy signal.

Abstract: To achieve, by a simple circuit configuration, a DRAM that permits refresh current to be effectively reduced by selectively setting refresh cycles. A memory cell array is divided into 64 subarrays, and each subarray is further divided into 8 blocks. A refresh cycle control circuit has a fuse circuit for setting a frequency dividing ratio of 1 or 1/2, a frequency divider that divides the frequency of a predecode signal by the set frequency dividing ratio, fuse circuits for setting a frequency dividing ratio of 1 or 1/4, and frequency dividers for dividing predecode signals by the set frequency dividing ratio. The refresh cycle control circuit is capable of setting a 64-ms or 128-ms refresh cycle for the 64 subarrays and a 64-ms or 256-ms refresh cycle for 512 blocks.

Abstract: Pseudo SRAM capable of arbitrating refresh requests with external access requests is provided. An access waiting circuit 20 for generating an access waiting signal /ECP in response to an external access request signal /CE or the like, an access activating circuit 21 for generating an access activating signal /AE in response to L level of the access waiting signal /ECP and H level of a busy signal /BUSY, a refresh waiting circuit 22 for generating a refresh waiting signal /REFP in response to a refresh request signal /REFT, and a refresh activating circuit 23 for generating a refresh activating signal /REFE in response to H level of the access waiting signal /ECP, L level of the refresh waiting signal /REFP, and H level of the busy signal /BUSY are provided. An array control circuit 12 performs an access operation in response to the access activating signal /AE, and performs the refresh operation in response to the refresh activating signal /REFE.