Abstract: A logic circuit design apparatus capable of designing scan circuits for uses peculiar to the logic circuit and scan circuits for test pattern generation simplification with ease is disclosed. The logic circuit design apparatus comprises a storage part, an acquisition part, a user resister design part, and a data chain design part. The storage part stores a circuit data of a logic circuit whose logic design for normal operation. The acquisition part acquires a design data which specifies a user resister that is a scan circuit to be designed on the logical circuit whose circuit data is stored in the storage part. The user resister design part designs a user resister corresponding the design data acquired by the acquisition part. The data chain design part designs a data chain which is a scan circuit for test pattern generation simplification by utilizing the user register designed by the user register design part.

Abstract: In a method for managing design data regarding an electronic circuit in order to design and analyze the electronic circuit, the design data is arranged according to a hierarchical-layer module structure. The design data in each of hierarchical layers of the hierarchical-layer module structure is divided into objects. The objects together for each of the hierarchical layers are connected together and the objects are connected together over the hierarchical layers. The design data including design data having different items and design data having different data lengths is integrally managed.