Abstract: A solid-state imaging device includes plural pixel cells, arranged in a matrix, each of which includes a photodiode that photoelectrically converts incident light. The solid-state imaging devices also includes a transferring transistor that transfers a charge generated by the photodiode, a floating diffusion that accumulates the transferred charge, a reset transistor that resets a potential of said floating diffusion, and an amplifying transistor that converts the charge accumulated in the floating diffusion into a voltage.

Abstract: A solid-state image pickup device includes: plural pixel cells that are two-dimensionally arrayed, the pixel cell including a photoelectric conversion element and an amplification transistor; plural vertical signal lines; at least two reference current source circuits that includes a reference transistor; and plural load transistors each of which is connected to the vertical signal line, the load transistor constituting a current mirror in conjunction with the reference transistor. The load transistor and the reference transistor are grounded to a common ground line in different positions, and, in at least two position, a distance between connection points at which the load transistor and the reference transistor, which constitute the current mirror, are grounded to the ground line is shorter than a distance between connection points of the load transistors adjacent to each other on the ground line.

Abstract: A solid-state imaging device includes: plural pixel cells, arranged in a matrix, each of which includes a photodiode which photoelectrically converts incident light, a transferring transistor which transfers a charge generated by the photodiode, a floating diffusion which accumulates the transferred charge, a reset transistor which resets a potential of said floating diffusion, and an amplifying transistor which converts the charge accumulated in the floating lo diffusion into a voltage; column signal lines each connected to associated ones of plurality of amplifying transistors including the amplifying transistor corresponding to a corresponding one of columns having the associated plurality of pixel cells; and a voltage control circuit which increases a voltage of the column signal line to a predetermined voltage between the reset of the potential by the reset transistor and the transfer of the charge by the transferring transistor.

Abstract: In a MOS solid-state imaging device, each of a plurality of pixel cells has a charge holding unit 305. In order to reset the signal charge accumulated in the charge holding unit 305 in each pixel cell in an n-th row, the reset pulse supplied to the gate electrode of the reset transistor is switched to the high potential level Hi. Under this state, the reference voltage source VDDCELL is switched to the low potential level Lo. In response, the reset pulse n temporarily drops toward Lo because of the coupling capacity 308. The reset pulse n is switched to Lo after its potential rises back to Hi.

Abstract: A variable gain amplifier includes a plurality of element circuits each having an output current that increases at a constant rate with a change in a variable control voltage, voltages that increase in steps of the change being respectively supplied to the plurality of element circuits as their reference voltages and the control voltage being supplied to each of the plurality of element circuits, multipliers for multiplying the output currents from the plurality of element circuits by one another, and an amplifier for carrying out a variable gain amplification based on an output current from the multipliers. The variable gain amplifier can suppress any change in the characteristics thereof due to temperature compensation of the characteristics and variations in manufacturing of transistors, and carry out a linear gain control operation on the control voltage when the gain is expressed in a logarithm.

Abstract: In a &pgr;/2 phase shifter, first and second signals and first and second inverted signals are produced based on input signals. The first and second signals have the same amplitude and are out of phase from each other, and the first and second inverted signals respectively correspond to the first and second signals with their respective phases inverted. A first output signal is produced by adding the first signal and the second signal, and a second output signal is produced by adding the first signal and the second inverted signal. Since the first and second signals have the same amplitude, the first output signal and the second output signal respectively correspond to diagonal lines of a rhombus formed by a vector representing the first signal and a vector representing the second signal. Accordingly, the phase difference between the first and second output signals of the &pgr;/2 phase shifter is accurately set to &pgr;/2 even when the phase difference between the first and second signals is not &pgr;/2.