Abstract: The disclosure provides an aqueous dispersion that can provide a film having excellent weather resistance and excellent hardness and that has excellent dispersion stability. The aqueous dispersion contains a fluorine-containing polymer that contains: a polymerized unit (a) based on a fluorine-containing monomer; a polymerized unit (b) based on a carboxy group-containing monomer; and a polymerized unit (c) based on a hydroxy group-containing monomer. The polymerized unit (b) is contained in an amount of 4.0 to 14.0 mol % of all polymerized units and the polymerized unit (c) is contained in an amount of 14.0 to 35.0 mol % of all polymerized units.

Abstract: A combustible gas that enables reducing an amount of CO2 generated at a time of cutting an object is provided. A combustible gas for use as a combustion gas for gas cutting of an object contains ethylene at a concentration of greater than 0% by volume and less than 18% by volume, with the remainder being hydrogen and unavoidable impurities. The combustible gas is preferably encapsulated in a container, and a pressure in the container at 35° C. is preferably 1 MPa or more and 50 MPa or less. A concentration of the unavoidable impurities is preferably 1.0% by volume or less. The object is preferably steel.

Abstract: When performing a process in an object to be authenticated, there is a case that an execution result depends on the reference data value to be referenced and remains undefined. When the execution result is undefined and a process after that references the execution result, the execution results may have different values. As a result, the execution results cannot be compared and authentication cannot be continued. There is provided an authentication device for giving the same test pattern to an object to be authenticated and an expectation value generation device, performing simulation, and comparing the execution results. Data being simulated is extracted. According to the analysis result of the extracted data, the simulation is controlled. Alternatively, simulation after the undefined result is obtained is controlled. Thus, it is possible to prevent execution of a process which becomes an undefined result.

Abstract: For detecting a failure of a logic circuit 11 provided in a semiconductor integrated circuit due to deterioration with age, or the like, there is provided a reference-producing circuit 12 using a logic different from the logic of the logic circuit 11. The reference-producing circuit 12 produces an abnormal/normal determination reference S for a predetermined output signal out output from the logic circuit 11. The reference-producing circuit 12 is made from only a portion of the logic of the logic circuit 11 or with a logic totally different from the logic of the logic circuit 11 to produce the determination reference S, so that the circuit scale of the reference-producing circuit 12 is smaller than that of the logic circuit 11. The determination reference S from the reference-producing circuit 12 and the output signal out from the logic circuit 11 are compared with each other by a determination circuit 13.

Abstract: For detecting a failure of a logic circuit 11 provided in a semiconductor integrated circuit due to deterioration with age, or the like, there is provided a reference-producing circuit 12 using a logic different from the logic of the logic circuit 11. The reference-producing circuit 12 produces an abnormal/normal determination reference S for a predetermined output signal out output from the logic circuit 11. The reference-producing circuit 12 is made from only a portion of the logic of the logic circuit 11 or with a logic totally different from the logic of the logic circuit 11 to produce the determination reference S, so that the circuit scale of the reference-producing circuit 12 is smaller than that of the logic circuit 11. The determination reference S from the reference-producing circuit 12 and the output signal out from the logic circuit 11 are compared with each other by a determination circuit 13.

Abstract: A semiconductor integrated circuits can send and receive signals to and form a configuration memory. The semiconductor integrated circuits is provided therein wiht an instruction memory, an instruction storage portion that stores reserved instructions as F instructions, and stores the substantially equivalent processing contents to the F instructions as substitute instructions for processing by the CPU, a pre-fetch portion, a history storage portion, a diagnosing portion for diagnosing the types of instructions, a reprogramming control portion for reprogramming the instructions, a CPU, an FPGA, a configuration data memory, a built-in memory, and a configuration data tag. When the configuration data of the F instruction does not exist in the FPGA, the substantially equivalent processing by FPGA is executed by the CPU by making use of the substitute instructions.

Abstract: A semiconductor integrated circuits can send and receive signals to and form a configuration memory. The semiconductor integrated circuits is provided therein wiht an instruction memory, an instruction storage portion that stores reserved instructions as F instructions, and stores the substantially equivalent processing contents to the F instructions as substitute instructions for processing by the CPU, a pre-fetch portion, a history storage portion, a diagnosing portion for diagnosing the types of instructions, a reprogramming control portion for reprogramming the instructions, a CPU, an FPGA, a configuration data memory, a built-in memory, and a configuration data tag. When the configuration data of the F instruction does not exist in the FPGA, the substantially equivalent processing by FPGA is executed by the CPU by making use of the substitute instructions.

Abstract: An electromagnetic disturbance analysis method for analyzing an external noise to a semiconductor integrated circuit includes an impedance extraction step of extracting impedance information on the power wiring in the target semiconductor integrated circuit or the power wiring in the semiconductor integrated circuit and the external power wiring of the semiconductor integrated circuit, an equivalent circuit creating step of creating an equivalent circuit from the impedance information, and an analysis step of supplying a noise waveform externally and analyzing the influence of the noise on the semiconductor integrated circuit.

Abstract: An electromagnetic disturbance analysis method for analyzing an external noise to a semiconductor integrated circuit includes an impedance extraction step of extracting impedance information on the power wiring in the target semiconductor integrated circuit or the power wiring in the semiconductor integrated circuit and the external power wiring of the semiconductor integrated circuit, an equivalent circuit creating step of creating an equivalent circuit from the impedance information, and an analysis step of supplying a noise waveform externally and analyzing the influence of the noise on the semiconductor integrated circuit.

Abstract: A semiconductor integrated circuits can send and receive signals to and form a configuration memory. The semiconductor integrated circuits is provided therein wiht an instruction memory, an instruction storage portion that stores reserved instructions as F instructions, and stores the substantially equivalent processing contents to the F instructions as substitute instructions for processing by the CPU, a pre-fetch portion, a history storage portion, a diagnosing portion for diagnosing the types of instructions, a reprogramming control portion for reprogramming the instructions, a CPU, an FPGA, a configuration data memory, a built-in memory, and a configuration data tag. When the configuration data of the F instruction does not exist in the FPGA, the substantially equivalent processing by FPGA is executed by the CPU by making use of the substitute instructions.

Abstract: There is provided a correlation degree operation apparatus in which the search area is readily extensible, in which a high-speed process can be assured even though the search area is extended, and which can be formed in a simple arrangement. The search area memory stores the picture element data of a search area including ((m.times.M).times.L) candidate blocks. The correlation degree operation unit executes an operation of a degree of correlation between a reference picture block and each of the candidate blocks, with the use of picture element data supplied from the search area memory, this operation being executed by a pipeline process for each candidate block group composed of (M.times.L) candidate blocks. The search area memory has the function of supplying four picture element data at the same clock cycle. This enables the correlation degree operation unit to continuously execute the pipeline processes for the candidate block groups.

Abstract: A layout area includes a clock interconnection consisting of an upward interconnection and a downward interconnection. The upward interconnection extends from the output terminal of a clock buffer which receives an external clock signal to a turning point while passing along the vicinity of a plurality of flip-flops. The downward interconnection extends from the turning point to a free end, reversing along the upward interconnection. Clock branch circuits are provided in the vicinity of the flip-flops. The clock branch circuits have a function of letting a third clock signal make a transition when the sum of the time integral of a first clock signal on the upward interconnection and the time integral of a second clock signal on the downward interconnection has become equal to the time integral for one pulse of one of the first clock signal and the second clock signal.