Abstract: A testing apparatus for a memory IC with a redundancy circuit includes a first memory, a counter, a second memory and a comparator. The first memory has a memory area for row addresses or column addresses of a target memory with a redundancy circuit, and stores row addresses or column addresses of defective bits of the target memory. The counter counts the number of defective-bit containing rows or columns of the target memory. The second memory stores a number of rows or columns of spare memory cells provided in the redundancy circuit. The comparator compares a count value of the counter with the number stored in the second memory. When the count value of the counter exceeds the number of rows or columns of spare memory cells stored in the second memory, it is considered unrepairable and test is terminated.

Abstract: A pattern generator includes a control unit, an address generation unit, and a data memory unit. The control unit has a plurality of control memories for storing information of the scanning order of addresses, the control unit outputting an address in accordance with the information stored in the control memories. The address generation unit has a plurality of address control memories for storing information used for controlling to generate addresses, the address control memories being provided in correspondence with the control memories, a data multiplexer for selecting and outputting the information outputted from the plurality of address control memories, and an address control unit for controlling to generate the addresses in accordance with the information outputted from the data multiplexer, the address generation unit outputting the addresses generated upon control by the address control unit.

Abstract: A memory device is provided with first and second memories. Two groups of data are loaded into the first and second memories, through a data buffer register. The same address information is applied to the first and second memories and the information is read out from the first and second memories. The two groups of the data read out in parallel are applied to a data multiplexer which in turn converts the parallel information into the serial one.

Abstract: The input test information and the expected value information stored in a main memory are stored in first and second local memories through first and second write circuits. The first and second local memories are addressed with given different phases by first and second address control circuits, respectively, so that the first and second local memories produce the information in parallel fashion with given periods. The information outputted are applied to a data multiplexer. Upon the application of the information, the data multiplexer converts the information inputted parallely thereto into the serial information which in turn is applied to the input pattern format control circuit and GO/NO GO judgement circuit. The response information from the integrated circuit to be tested is applied to the GO/NO GO judgement circuit where GO or NO GO of the integrated circuit is judged.

Abstract: Input test information and the expected value information stored in a main memory are stored in first and second local memories through first and second write circuits. The first and second local memories are addressed with given different phases by address control circuits, respectively, so that the first and second local memories produce the information in parallel fashion within given periods. The information outputted are temporarily stored into a data register which in turn applies it to the data multiplexer. Upon the application of the information, the data multiplexer converts the information inputted parallel thereto into serial information which in turn is applied to the input pattern format control circuit and a GO/NO GO judgment circuit. The response information from the integrated circuit to be tested is applied to the GO/NO GO judgment circuit where GO or NO GO of the integrated circuit is judged.