Patents by Inventor Hisatsugu Kurita

Hisatsugu Kurita has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7247583
    Abstract: A method for manufacturing a strained silicon wafer, having steps of a first step of preparing a single crystal silicon substrate, a second step of forming a graded SiGe layer on the substrate, the graded SiGe layer having a first Ge composition ratio increased stepwisely from 5 to 60% at atomic ratio, a third step of forming a SiGe constant composition layer on the graded SiGe layer, the SiGe constant composition layer having a Ge composition ratio substantially equal to the Ge composition ratio on a surface of the-graded SiGe layer and a fourth step of forming a strained Si layer on the SiGe constant composition layer. The second through fourth steps are performed under the reduced pressure atmosphere while the single crystal silicon substrate is rotated in a circumferential direction at a rate from 300 rpm to 1500 rpm.
    Type: Grant
    Filed: January 21, 2005
    Date of Patent: July 24, 2007
    Assignee: Toshiba Ceramics Co., Ltd.
    Inventors: Hisatsugu Kurita, Masato Igarashi, Takeshi Senda, Koji Izunome
  • Patent number: 7226513
    Abstract: This invention provides a cleaning method of silicon wafer for obtaining a silicon wafer in which micro roughness thereof under spatial frequency of 20/?m is 0.3 to 1.5 nm3 in terms of power spectrum density, by passing a process of oxidizing the silicon wafer with ozonized water and a process of cleaning said oxidized silicon wafer with hydrofluoric acid. Consequently, it is possible to remove surface adhering pollutant such as particles and metallic foreign matter with the surface structure of silicon wafer flattened up to atomic level by annealing maintained.
    Type: Grant
    Filed: August 22, 2003
    Date of Patent: June 5, 2007
    Assignee: Toshiba Ceramics Co., Ltd.
    Inventors: Hisatsugu Kurita, Manabu Hirasawa, Hiromi Nagahama, Koji Izumome, Takao Ino, Jyunsei Yamabe, Naoya Hayamizu, Naoaki Sakurai
  • Patent number: 7060597
    Abstract: A manufacturing method for a silicon substrate having a strained layer, has steps of forming a plurality of atomic steps having a height of 0.1 nm or more on the surface of a silicon substrate, forming a plurality of terraces having a width of 0.1 ?m or more between the plurality of atomic steps and forming a SiGe layer or a SiGe layer and a Si layer on the silicon substrate.
    Type: Grant
    Filed: May 18, 2004
    Date of Patent: June 13, 2006
    Assignee: Toshiba Ceramics Co., Ltd.
    Inventors: Hisatsugu Kurita, Masato Igarashi, Takeshi Senda, Koji Izunome
  • Publication number: 20050170664
    Abstract: A method for manufacturing a strained silicon wafer, having steps of a first step of preparing a single crystal silicon substrate, a second step of forming a graded SiGe layer on the substrate, the graded SiGe layer having a first Ge composition ratio increased stepwisely from 5 to 60% at atomic ratio, a third step of forming a SiGe constant composition layer on the graded SiGe layer, the SiGe constant composition layer having a Ge composition ratio substantially equal to the Ge composition ratio on a surface of the-graded SiGe layer and a fourth step of forming a strained Si layer on the SiGe constant composition layer. The second through fourth steps are performed under the reduced pressure atmosphere while the single crystal silicon substrate is rotated in a circumferential direction at a rate from 300 rpm to 1500 rpm.
    Type: Application
    Filed: January 21, 2005
    Publication date: August 4, 2005
    Inventors: Hisatsugu Kurita, Masato Igarashi, Takeshi Senda, Koji Izunome
  • Publication number: 20040235274
    Abstract: A manufacturing method for a silicon substrate having a strained layer, has steps of forming a plurality of atomic steps having a height of 0.1 nm or more on the surface of a silicon substrate, forming a plurality of terraces having a width of 0.1 &mgr;m or more between the plurality of atomic steps and forming a SiGe layer or a SiGe layer and a Si layer on the silicon substrate.
    Type: Application
    Filed: May 18, 2004
    Publication date: November 25, 2004
    Applicant: TOSHIBA CERAMICS CO., LTD.
    Inventors: Hisatsugu Kurita, Masato Igarashi, Takeshi Senda, Koji Izunome
  • Publication number: 20040045580
    Abstract: This invention provides a cleaning method of silicon wafer for obtaining a silicon wafer in which micro roughness thereof under spatial frequency of 20/&mgr;m is 0.3 to 1.5 nm3 in terms of power spectrum density, by passing a process of oxidizing the silicon wafer with ozonized water and a process of cleaning said oxidized silicon wafer with hydrofluoric acid. Consequently, it is possible to remove surface adhering pollutant such as particles and metallic foreign matter with the surface structure of silicon wafer flattened up to atomic level by annealing maintained.
    Type: Application
    Filed: August 22, 2003
    Publication date: March 11, 2004
    Applicant: TOSHIBA CERAMICS CO.,LTD.
    Inventors: Hisatsugu Kurita, Manabu Hirasawa, Hiromi Nagahama, Koji Izumome, Takao Ino, Jyunsei Yamabe, Naoya Hayamizu, Naoaki Sakurai