Patents by Inventor Hisatsugu Shirai

Hisatsugu Shirai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7270920
    Abstract: A method of fabricating a semiconductor device includes an exposure step conducted by using a reticle. The method includes the steps of exposing a first pattern on a wafer by using a first reticle having a first reticle error, and exposing a second pattern on the wafer in alignment with the first pattern by using a second reticle having a second error, wherein the step of exposing the second pattern uses a reticle having a reticle error that satisfies a requirement of critical alignment error as the second reticle, the critical alignment error being determined from a design rule applied to the wafer, the critical alignment error being further determined with reference to the first reticle error of the first reticle.
    Type: Grant
    Filed: March 10, 2005
    Date of Patent: September 18, 2007
    Assignee: Fujitsu Limited
    Inventor: Hisatsugu Shirai
  • Patent number: 7226866
    Abstract: A reticle manufacturing method comprises a step of retreating side surfaces of a lift-off pattern to reduce an area of a wide pattern portion, a step of forming a wide convex pattern and a narrow convex pattern by etching a glass substrate (transparent substrate) while using a second mask pattern as a mask, a step of reducing an area of a first wide mask portion, a step of reducing at least an area of a second wide mask portion smaller than an area of the first wide mask portion, and a step of reducing an area of a wide light shielding portion by etching the wide light shielding portion while using the first wide mask portion as a mask.
    Type: Grant
    Filed: December 29, 2004
    Date of Patent: June 5, 2007
    Assignee: Fujitsu Limited
    Inventors: Hisatsugu Shirai, Kiyoshi Ozawa
  • Publication number: 20060132776
    Abstract: A method of fabricating a semiconductor device includes an exposure step conducted by using a reticle. The method includes the steps of exposing a first pattern on a wafer by using a first reticle having a first reticle error, and exposing a second pattern on the wafer in alignment with the first pattern by using a second reticle having a second error, wherein the step of exposing the second pattern uses a reticle having a reticle error that satisfies a requirement of critical alignment error as the second reticle, the critical alignment error being determined from a design rule applied to the wafer, the critical alignment error being further determined with reference to the first reticle error of the first reticle.
    Type: Application
    Filed: March 10, 2005
    Publication date: June 22, 2006
    Applicant: FUJITSU LIMITED
    Inventor: Hisatsugu Shirai
  • Publication number: 20050266318
    Abstract: A reticle manufacturing method comprises a step of retreating side surfaces of a lift-off pattern to reduce an area of a wide pattern portion, a step of forming a wide convex pattern and a narrow convex pattern by etching a glass substrate (transparent substrate) while using a second mask pattern as a mask, a step of reducing an area of a first wide mask portion, a step of reducing at least an area of a second wide mask portion smaller than an area of the first wide mask portion, and a step of reducing an area of a wide light shielding portion by etching the wide light shielding portion while using the first wide mask portion as a mask.
    Type: Application
    Filed: December 29, 2004
    Publication date: December 1, 2005
    Applicant: FUJITSU LIMITED
    Inventors: Hisatsugu Shirai, Kiyoshi Ozawa
  • Patent number: 5175128
    Abstract: A method for fabricating a semiconductor device comprises the steps of defining a plurality of regions on a substrate, exposing a first pattern that extends over a plurality of such regions such that the first pattern is exposed on the plurality of regions simultaneously, and exposing a plurality of second patterns that are identical in size and shape and isolated from each other, consecutively for each of the plurality of regions.
    Type: Grant
    Filed: November 8, 1991
    Date of Patent: December 29, 1992
    Assignee: Fujitsu Limited
    Inventors: Taiji Ema, Hisatsugu Shirai, Katsuyoshi Kobayashi, Masao Taguchi
  • Patent number: 5132252
    Abstract: A method for preventing contamination caused by residues of etched off patterns etched by photolithographic etching. A considerable amount of small contamination spots on a semiconductor chip are found to be caused by tiny residues of etched off patterns. These residues are formed primarily around the periphery of device areas and mark patterns when their outsides are etched off. The occurence of such residues of etching is increased by anisotropic etching. These residues are dislodged by succeeding steps of the pattern making process, and disperse over the substrate causing small contamination spots. To avoid the detrimental effects of the etching residues, the edges of the mark patterns and device areas are covered with an edge cover which is formed in a step to following the pattern etching process.
    Type: Grant
    Filed: April 25, 1989
    Date of Patent: July 21, 1992
    Assignees: Fujitsu Limited, Kyushu Fujitsu Electronics Limited
    Inventors: Hidehiko Shiraiwa, Hisatsugu Shirai, Nobuhiro Takahashi, Shinichi Nomura