Abstract: According to one embodiment, an electronic device includes a non-volatile memory; a controller that is electrically connected to the non-volatile memory and configured for accessibility to a memory space including a plurality of management areas in a host; at least one counter that is provided for each of the plurality of management areas and configured to increment a count value each time data is stored in the corresponding one of the plurality of management areas; and a circuit configured to generate a first value relating to integrity of the data for each management area based on the count value and the data. The controller is configured to store the data and the first value associated with the data.

Abstract: A processing device includes a memory, a first processor configured to execute software fetched from the memory, a second processor configured to perform a verification of the software stored in the memory, and a controller configured to control a fetch of the software from the memory by the first processor according to the verification performed by the second processor. The controller prohibits the fetch by the first processor until the verification of the software performed by the second processor is successful and permits the fetch by the first processor when the verification of the software performed by the second processor is successful.

Abstract: A processing device includes a memory, a first processor configured to execute software fetched from the memory, a second processor configured to perform a verification of the software stored in the memory, and a controller configured to control a fetch of the software from the memory by the first processor according to the verification performed by the second processor. The controller prohibits the fetch by the first processor until the verification of the software performed by the second processor is successful and permits the fetch by the first processor when the verification of the software performed by the second processor is successful.

Abstract: A secure memory controller includes a memory unit and a controller. The memory unit stores the information of the predetermined scenario in accordance with an application to be executed. The controller gives the right to access the memory area based on the set scenario. The controller judges whether the bus master which is requesting an access to the memory area has the right to access.

Abstract: The information processing apparatus includes a CPU, a memory connected to the CPU 2 via a bus, an external device configured to perform predetermined processing, an MMU, and a DMAC. The DMAC transfers input data from the memory based on a physical address of the memory set as a physical address of the input data, and output data to the memory based on a physical address of the memory set as a physical address of the output data. The external device obtains from the MMU a physical address corresponding to a virtual address of target data, and obtains from the MMU a physical address corresponding to a virtual address of result data. The external device sets the obtained physical addresses of the target data and the result data as physical addresses of the input data and the output data, respectively.

Abstract: There is provided with an information processing apparatus, including: a CPU; a register that stores a task ID or a process ID that identifying a task or a process; and a cache memory that records data specified by the CPU on a cache line corresponding to a memory address specified by the CPU, and writes a task ID or a process ID stored in the register in one part of a tag that manages the cache line as an owner ID; wherein the CPU executes a cache control instruction instructing to write back only cache lines having an owner ID that is the same as a task ID or a process ID in the register.