Patents by Inventor Hisaya Mori

Hisaya Mori has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20020118007
    Abstract: A BOST (built-off self-test) board has a connector, a substrate for use with a BOST board, and an external self-test circuit. The external self-test circuit has an ADC (analog-to-digital converter)/DAC (digital-to-analog converter) measurement section and a DSP (digital signal processor). In accordance with a control signal input by way of a specific terminal provided in a connector, the ADC/DAC measurement section transmits a predetermined test signal to the specific terminal provided in the connector. Further, in response to the test signal, the ADC/DAC measurement section receives a response signal input to the specific terminal provided in the connector. The DSP analysis section analyzes the response signal, thereby determining whether or not the response signal is an appropriate signal. Further, the DSP analysis section transmits, to the specific terminal provided in the connector, a test result signal indicating whether or not the response signal is appropriate.
    Type: Application
    Filed: August 13, 2001
    Publication date: August 29, 2002
    Applicant: MITSUBISHI DENKI KABUSHIKI KAISHA
    Inventors: Hisaya Mori, Shinji Yamada, Teruhiko Funakura
  • Publication number: 20020118017
    Abstract: There are provided a test apparatus and a test method for testing a semiconductor integrated circuit which facilitate control of a BOST device and improve the versatility of the BOST device. There is provided an interface for exchanging signals between a BOST device and an external controller. A test control signal and a test result analysis signal are exchanged by means of the interface, thus effecting a test and analysis of the test.
    Type: Application
    Filed: August 13, 2001
    Publication date: August 29, 2002
    Applicant: Mitsubishi Denki Kabushiki Kaisha and Ryoden Semiconductor System Engineering Corporation
    Inventors: Hisaya Mori, Shinji Yamada, Teruhiko Funakura
  • Publication number: 20020105352
    Abstract: A test ancillary device with data memory and an analysis section is disposed in the vicinity of a test circuit board. The data memory is divided into two memory sections such that, when digital test data are stored in one memory section, the digital test data that have already been stored in the other memory section are loaded for analysis purpose.
    Type: Application
    Filed: August 13, 2001
    Publication date: August 8, 2002
    Applicant: MITSUBISHI DENKI KABUSHIKI KAISHA
    Inventors: Hisaya Mori, Shinji Yamada, Teruhiko Funakura
  • Publication number: 20020105353
    Abstract: An external test ancillary device (BOST device) analyzes measured information output from a semiconductor integrated circuit and transmits a result of analysis to a semiconductor test apparatus. The external test ancillary device includes a DAC counter for generating input data; a digital-to-analog converter for converting the data output from the counter from a digital signal into an analog signal; an analog-to-digital converter which receives data output from the digital-to-analog converter by way of a loopback line and converts the data from an analog signal into a digital signal; a DSP analysis section for performing self-diagnostic operation on the basis of data output from the analog-to-digital converter; measured data memory, an address counter, and a data write control circuit.
    Type: Application
    Filed: August 13, 2001
    Publication date: August 8, 2002
    Applicant: MITSUBISHI DENKI KABUSHIKI KAISHA, and RYODEN SEMICONDUCTOR SYSTEM ENGINEERING CORPORATION
    Inventors: Hisaya Mori, Shinji Yamada, Teruhiko Funakura
  • Publication number: 20020107654
    Abstract: There is provided an apparatus and method of testing a semiconductor integrated circuit, which apparatus and method enable testing of various semiconductor integrated circuits having different characteristics, fulfillment of the function of generating DAC data, and adaptation of various analog characteristic tests. An input range of a BOST device is switchable in accordance with the level of a DAC of a DUT, so that the test apparatus can handle DUTs of different types having different analog output levels.
    Type: Application
    Filed: August 13, 2001
    Publication date: August 8, 2002
    Applicant: MITSUBISHI DENKI KABUSHIKI KAISHA
    Inventors: Hisaya Mori, Shinji Yamada, Teruhiko Funakura
  • Publication number: 20020108080
    Abstract: There are provided a test apparatus and method for testing a semiconductor integrated circuit which enables improvements in the ease of operation and convenience of a BOST device and shortening of a test time. Numeric codes are assigned to tests. A test apparatus is equipped with memory and an analysis section. A test requirement table—in which hardware requirements required for conducting a test are set on a per-numeric-code basis—is stored in the memory. Test requirements corresponding to a numeric code are read from the memory, whereupon a test is performed. The analysis section analyzes a digital test output and sends the result of analysis to an external controller.
    Type: Application
    Filed: August 13, 2001
    Publication date: August 8, 2002
    Applicant: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Hisaya Mori, Shinji Yamada, Teruhiko Funakura
  • Publication number: 20020106817
    Abstract: A semiconductor test apparatus includes an analog-to-digital converter for converting into a digital signal an analog output from a circuit under test; a test-apparatus-ADC-control-signal generation circuit for generating a control signal for the analog-to-digital converter in accordance with an activation signal entered from the outside; a measured data memory for storing, as measured data for each conversion, a signal output from the analog-to-digital converter; an address counter for generating an address signal for the measured data memory; a DAC counter for generating data to be input to the circuit under test; and a data write control circuit which produces, in response to a flag signal output from the analog-to-digital converter and representing that conversion is being performed, an update signal for the address counter, a memory write signal for the measured data memory, and an update signal for the DAC counter.
    Type: Application
    Filed: August 13, 2001
    Publication date: August 8, 2002
    Applicant: Mitsubishi Denki Kabushiki Kaisha and Ryoden Semiconductor System Engineering Corporation
    Inventors: Hisaya Mori, Shinji Yamada, Teruhiko Funakura
  • Publication number: 20020062200
    Abstract: To provide a tester for semiconductor integrated circuits that can test an A/D converter circuit and a D/A converter circuit in a mixed signal type semiconductor integrated circuit comprising an A/D converter circuit and a D/A converter circuit at high accuracy and at high speed. A test assisting device is provided in the vicinity of a testing circuit board on which a semiconductor integrated circuit to be tested is mounted. The test assisting device comprises a data circuit to supply analog test signals to the A/D converter circuit of the semiconductor integrated circuit to be tested, and digital test signals to the D/A converter circuit thereof, a measured data memory to store test outputs from the semiconductor integrated circuit to be tested, and an analyzer portion to analyze data stored in the measured data memory.
    Type: Application
    Filed: July 16, 2001
    Publication date: May 23, 2002
    Applicant: MITSUBISHI DENKI KABUSHIKI KAISHA
    Inventors: Hisaya Mori, Shinji Yamada, Teruhiko Funakura