Patents by Inventor Hisaya Okumura

Hisaya Okumura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5963785
    Abstract: In a semiconductor integrated circuit consisting of a plurality of semiconductor chips each having a plurality of islands, two or more bonding wires each having different potential are connected to bonding pads formed on the surface of semiconductor chips. The islands are isolated by a dielectric isolation region comprising polysilicon film and isolation film formed in an isolation groove. The polysilicon film is exposed at a dicing line region around the semiconductor chip and a surface of the polysilicon film is made highly resistive. If two or more bonding wires come into contact with the polysilicon film exposed at a peripheral region of the semiconductor chip to cause short circuit, parasitic conductance does not occur between two or more bonding wires because the peripheral region of the semiconductor chip has high resistivity, whereby variation in characteristics of the semiconductor integrated circuit can be suppressed.
    Type: Grant
    Filed: February 28, 1997
    Date of Patent: October 5, 1999
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Toshimitu Katoh, Yoshiaki Aizawa, Hisaya Okumura
  • Patent number: 5559466
    Abstract: A semiconductor relay has two output MOSFET pairs, each of which is series-connected with the other. Each MOSFET pair is comprised of two MOSFETs series-connected oppositely to each other, and these MOSFETs are controlled to turn on or off simultaneously. The semiconductor relay further includes a switch, which is inserted between the ground and the junction of the two MOSFET pairs. When these MOSFETs are in an off condition, said switch is closed in order to release electric charges accumulated on said MOSFETs and to increase the off-resistance of this semiconductor relay. On the other hand, when the MOSFETs are in an on condition, said switch is opened so as to connect both MOSFET pairs in series. As a result, a semiconductor relay having a high off-resistance can be obtained without increasing the on-resistance.
    Type: Grant
    Filed: July 25, 1994
    Date of Patent: September 24, 1996
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hisaya Okumura, Yoshiaki Aizawa
  • Patent number: 5408102
    Abstract: A photo-coupler apparatus has a light emitting diode, a photo-diode array, an output MOSFET which is driven by the photoelectromotive force generated by said photo-diode array, and a circuit for limiting the gate voltage of said output MOSFET below a certain value. Said limiting circuit includes a first resistor for detecting output currents, an NPN transistor, a second resistor, and a PNP transistor. In this structure, the voltages developed across the first and second resistors are used to drive the NPN and PNP transistors respectively. In addition, the NPN transistor is connected to the gate of said MOSFET through said second resistor. According to this structure, the gate voltage of the output MOSFET is kept below a certain value by being controlled with the PNP transistor which is driven by the NPN transistor. Thus, stable protection against excessive current is achieved. In addition, a resistor having a small value can be used as the first resistor so as to reduce the heat loss of this apparatus.
    Type: Grant
    Filed: January 13, 1994
    Date of Patent: April 18, 1995
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Hisaya Okumura