Patents by Inventor Hisayasu Nishino

Hisayasu Nishino has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5965895
    Abstract: A method for providing charged particle beam exposure onto an object having a plurality of chip areas with a plurality of aligning marks formed in correspondence to each of said chip areas. A charged particle beam is irradiated upon an object mounted on a mobile step based upon positions of the aligning marks. Actual positions of the alignment marks are detected and compared to the design positions of the alignment marks to determine approximate relationships which are used to calculate an actual position to perform exposure.
    Type: Grant
    Filed: November 4, 1997
    Date of Patent: October 12, 1999
    Assignee: Fujitsu Limited
    Inventors: Takamasa Satoh, Hiroshi Yasuda, Junichi Kai, Yoshihisa Oae, Hisayasu Nishino, Kiichi Sakamoto, Hidefumi Yabara, Isamu Seto, Masami Takigawa, Akio Yamada, Soichiro Arai, Tomohiko Abe, Takashi Kiuchi, Kenichi Miyazawa
  • Patent number: 5721432
    Abstract: To improve in the throughput of an exposure system, the setting time during a step change in the output of an amplifier is reduced by switching resistance between the amplifier and deflector, a glitch waveform generated during a step change in the output of a D/A converter at the preceding stage of the amplifier, is anticipated and is canceled out with a correction waveform, after the output of the D/A converter has settled, this output is sample held and the step change is interpolated at a smoothing circuit, the deflection area is increased by positioning a electrostatic deflector offset around the optical axis relative to another electrostatic deflector, the response speed of the main deflection is improved by adding auxiliary deflection coils of one or two turn, and the alignment time is reduced by combining the coordinate conversion in the wafer area and in the chip area.
    Type: Grant
    Filed: June 20, 1996
    Date of Patent: February 24, 1998
    Assignee: Fujitsu Limited
    Inventors: Takamasa Satoh, Hiroshi Yasuda, Junichi Kai, Yoshihisa Oae, Hisayasu Nishino, Kiichi Sakamoto, Hidefumi Yabara, Isamu Seto, Masami Takigawa, Akio Yamada, Soichiro Arai, Tomohiko Abe, Takashi Kiuchi, Kenichi Miyazawa
  • Patent number: 5719402
    Abstract: To improve the throughput of an exposure system, the setting time during a step change in the output of an amplifier is reduced by switching resistance between the amplifier and a deflector. A glitch waveform generated during a step change in the output of a D/A converter at the preceding stage of the amplifier is anticipated and is cancelled out with a correction waveform. After the output of the D/A converter has settled, this output is sample-held and the step change is interpolated with a smoothing circuit. The deflection area is increased by positioning an electrostatic deflector offset around the optical axis relative to another electrostatic deflector, and the response speed of the main deflection is improved by adding auxiliary deflection coils of one or two turns. The alignment time is reduced by combining the coordinate conversion in the wafer area and in the chip area.
    Type: Grant
    Filed: April 4, 1996
    Date of Patent: February 17, 1998
    Assignee: Fujitsu Limited
    Inventors: Takamasa Satoh, Hiroshi Yasuda, Junichi Kai, Yoshihisa Oae, Hisayasu Nishino, Kiichi Sakamoto, Hidefumi Yabara, Isamu Seto, Masami Takigawa, Akio Yamada, Soichiro Arai, Tomohiko Abe, Takashi Kiuchi, Kenichi Miyazawa
  • Patent number: 5546319
    Abstract: To improve in the throughput of an exposure system, the setting time during a step change in the output of an amplifier is reduced by switching resistance between the amplifier and a deflector, a glitch waveform generated during a step change in the output or a D/A converter at the preceding stage of the amplifier, is anticipated and is canceled out with a correction waveform, after the output of the D/A converter has settled, this output is sample held and the step change is interpolated at a smoothing circuit, the deflection area is increased by positioning a electrostatic deflector offset around the optical axis relative to another electrostatic deflector, the response speed of the main deflection is improved by adding auxiliary deflection coils of one or two turn, and the alignment time is reduced by combining the coordinate conversion in the wafer area and in the chip area.
    Type: Grant
    Filed: January 27, 1995
    Date of Patent: August 13, 1996
    Assignee: Fujitsu Limited
    Inventors: Takamasa Satoh, Hiroshi Yasuda, Junichi Kai, Yoshihisa Oae, Hisayasu Nishino, Kiichi Sakamoto, Hidefumi Yabara, Isamu Seto, Masami Takigawa, Akio Yamada, Soichiro Arai, Tomohiko Abe, Takashi Kiuchi, Kenichi Miyazawa
  • Patent number: 5404018
    Abstract: A charged particle beam exposure apparatus employs a main deflector made of electromagnetic coils and a subdeflector made of electrostatic deflection electrodes. An exposure method used for this apparatus is capable of shortening a wait time of the main deflector. The main deflector deflects a charged particle beam in a direction X, while the subdeflector deflects the beam around the deflecting position of the main deflector to expose an object to the beam. An area to be exposed on the object is divided into thin subfields such that the width, in an X-axis direction of each subfield, is approximately 1/3 the length in a Y-axis direction of the same.
    Type: Grant
    Filed: February 28, 1992
    Date of Patent: April 4, 1995
    Assignee: Fujitsu Limited
    Inventors: Hiroshi Yasuda, Yoshihisa Oae, Akio Yamada, Nobuyuki Yasutake, Hisayasu Nishino
  • Patent number: 5399872
    Abstract: A charged-particle beam exposure method is used for a charged-particle beam exposure apparatus equipped with a blanking aperture array plate in which columns are arranged side by side in a first direction, and each of the columns includes a plurality of blanking apertures arranged in a second direction substantially perpendicular to the first direction, a charged-particle beam being moved on a wafer in the first direction. The method includes the steps of (a) determining one of first and second axes of a pattern to be exposed to be a priority axis; (b) projecting an image of the blanking aperture array plate onto the wafer so that the priority axis is perpendicular to the second direction; and (c) deflecting the charged-particle beam so that the wafer is scanned in the direction of the priority axis.
    Type: Grant
    Filed: October 20, 1993
    Date of Patent: March 21, 1995
    Assignee: Fujitsu Limited
    Inventors: Hiroshi Yasuda, Junichi Kai, Hisayasu Nishino, Soichiro Arai, Yoshihisa Oae
  • Patent number: 5382800
    Abstract: A charged particle beam exposure method for deflecting a charged particle beam in a deflection system which includes electromagnetic deflection coils, includes the steps of (a) controlling the deflection system based on deflection data, and (b) generating heat at least a vicinity of the electromagnetic deflection coils so as to compensate for a change in heat generated from the electromagnetic deflection coils.
    Type: Grant
    Filed: January 4, 1993
    Date of Patent: January 17, 1995
    Assignee: Fujitsu Limited
    Inventors: Hisayasu Nishino, Akio Yamada, Yoshihisa Oae, Hiroshi Yasuda
  • Patent number: 5338939
    Abstract: A charged particle beam exposure method deflects a charged particle beam in a deflection system which includes electromagnetic deflection coils and an electromagnetic lens. The charged particle beam exposure method includes controlling the deflection system based on deflection data, and blocking heat radiation from at least the electromagnetic deflection coils by a partition so as to prevent the heat radiation from reaching the electromagnetic lens and to prevent heat conduction to the electromagnetic lens by the partition.
    Type: Grant
    Filed: May 26, 1993
    Date of Patent: August 16, 1994
    Assignee: Fujitsu Limited
    Inventors: Hisayasu Nishino, Akio Yamada, Yoshihisa Oae, Hiroshi Yasuda