Patents by Inventor Hisayasu Sato
Hisayasu Sato has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20120092065Abstract: The present invention intends to provide a filter circuit in which an area occupied by the circuit can be reduced by suppressing the scale of its circuit configuration while a predetermined vicinity disturbance wave rejection ratio is maintained and a communication semiconductor device using the same, the filter circuit filtering an analog signal and including a voltage/current conversion circuit for converting the analog signal from voltage to current, and a capacitor array which executes signal processing by charging/discharging the current converted by the voltage/current conversion circuit to/from plural capacitors, the capacitor array being so constructed that the plural capacitors are divided to plural stages so that signals averaged by the capacitor on a preceding stage are accumulated in the capacitor on a next stage successively.Type: ApplicationFiled: December 22, 2011Publication date: April 19, 2012Applicant: Renesas Electronics CorporationInventors: Tomohiro SANO, Takaya Maruyama, Hisayasu Sato
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Patent number: 8116715Abstract: The present invention intends to provide a filter circuit in which an area occupied by the circuit can be reduced by suppressing the scale of its circuit configuration while a predetermined vicinity disturbance wave rejection ratio is maintained and a communication semiconductor device using the same, the filter circuit filtering an analog signal and including a voltage/current conversion circuit for converting the analog signal from voltage to current, and a capacitor array which executes signal processing by charging/discharging the current converted by the voltage/current conversion circuit to/from plural capacitors, the capacitor array being so constructed that the plural capacitors are divided to plural stages so that signals averaged by the capacitor on a preceding stage are accumulated in the capacitor on a next stage successively.Type: GrantFiled: August 25, 2008Date of Patent: February 14, 2012Assignee: Renesas Electronics CorporationInventors: Tomohiro Sano, Takaya Maruyama, Hisayasu Sato
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Publication number: 20090068976Abstract: The present invention intends to provide a filter circuit in which an area occupied by the circuit can be reduced by suppressing the scale of its circuit configuration while a predetermined vicinity disturbance wave rejection ratio is maintained and a communication semiconductor device using the same, the filter circuit filtering an analog signal and including a voltage/current conversion circuit for converting the analog signal from voltage to current, and a capacitor array which executes signal processing by charging/discharging the current converted by the voltage/current conversion circuit to/from plural capacitors, the capacitor array being so constructed that the plural capacitors are divided to plural stages so that signals averaged by the capacitor on a preceding stage are accumulated in the capacitor on a next stage successively.Type: ApplicationFiled: August 25, 2008Publication date: March 12, 2009Inventors: Tomohiro SANO, Takaya Maruyama, Hisayasu Sato
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Patent number: 7382175Abstract: A frequency mixer includes a first N channel MOS transistor, second and third N channel MOS transistors constituting a local oscillator signal differential pair, and having substantially identical properties, a first load, and a second load. The first N channel MOS transistor receives an RF signal at its gate. A local oscillator signal is applied to the gates of the second and third N channel MOS transistors. The drain current of the second and third N channel MOS transistors is output to the drain of the first N channel MOS transistor. An amplitude-current conversion circuit receives the RF signal and provides an output current to the drain of the first N channel MOS transistor to decrease monotonously the output current with respect to the amplitude of the RF signal.Type: GrantFiled: March 18, 2005Date of Patent: June 3, 2008Assignee: Renesas Technology Corp.Inventors: Takaya Maruyama, Hisayasu Sato
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Patent number: 7362194Abstract: An oscillator circuit is formed of a differential LC resonant circuit formed of an L load differential circuit including inductance-variable portions and a capacitor element, and a positive feedback circuit formed of N-channel MOS transistors. The inductance-variable portion is configured to vary the inductance by selecting a plurality of switch circuits arranged between a plurality of arbitrary positions on a spiral interconnection layer and the input/output terminal, and thereby can control an oscillation frequency. The inductance-variable portions form an inductor pair when the switch circuit among the switch circuits coupled between the first input/output terminals is turned on together with the switch circuit.Type: GrantFiled: February 20, 2007Date of Patent: April 22, 2008Assignee: Renesas Technology Corp.Inventors: Hiroshi Komurasaki, Tomohiro Sano, Hisayasu Sato, Toshio Kumamoto, Yasushi Hashizume
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Publication number: 20070146089Abstract: An oscillator circuit is formed of a differential LC resonant circuit formed of an L load differential circuit including inductance-variable portions and a capacitor element, and a positive feedback circuit formed of N-channel MOS transistors. The inductance-variable portion is configured to vary the inductance by selecting a plurality of switch circuits arranged between a plurality of arbitrary positions on a spiral interconnection layer and the input/output terminal, and thereby can control an oscillation frequency. The inductance-variable portions form an inductor pair when the switch circuit among the switch circuits coupled between the first input/output terminals is turned on together with the switch circuit.Type: ApplicationFiled: February 20, 2007Publication date: June 28, 2007Inventors: Hiroshi Komurasaki, Tomohiro Sano, Hisayasu Sato, Toshio Kumamoto, Yasushi Hashizume
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Patent number: 7202754Abstract: An oscillator circuit is formed of a differential LC resonant circuit formed of an L load differential circuit including inductance-variable portions and a capacitive element, and a positive feedback circuit formed of N-channel MOS transistors. The inductance-variable portion is configured to vary the inductance by selecting a plurality of switch circuits arranged between a plurality of arbitrary positions on a spiral interconnection layer and the input/output terminal, and thereby can control an oscillation frequency. The inductance-variable portions form an inductor pair when the switch circuit among the switch circuits coupled between the first input/output terminals is turned on together with the switch circuit.Type: GrantFiled: November 17, 2005Date of Patent: April 10, 2007Assignee: Renesas Technology Corp.Inventors: Hiroshi Komurasaki, Tomohiro Sano, Hisayasu Sato, Toshio Kumamoto, Yasushi Hashizume
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Publication number: 20060071732Abstract: An oscillator circuit is formed of a differential LC resonant circuit formed of an L load differential circuit including inductance-variable portions and a capacitive element, and a positive feedback circuit formed of N-channel MOS transistors. The inductance-variable portion is configured to vary the inductance by selecting a plurality of switch circuits arranged between a plurality of arbitrary positions on a spiral interconnection layer and the input/output terminal, and thereby can control an oscillation frequency. The inductance-variable portions form an inductor pair when the switch circuit among the switch circuits coupled between the first input/output terminals is turned on together with the switch circuit.Type: ApplicationFiled: November 17, 2005Publication date: April 6, 2006Applicant: RENESAS TECHNOLOGY CORPORATIONInventors: Hiroshi Komurasaki, Tomohiro Sano, Hisayasu Sato, Toshio Kumamoto, Yasushi Hashizume
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Publication number: 20050208922Abstract: A frequency mixer includes a first N channel MOS transistor, second and third N channel MOS transistors constituting a local oscillator signal differential pair, and having substantially identical properties, a first load, and a second load. The first N channel MOS transistor receives an RF signal at its gate. A local oscillator signal is applied to the gates of the second and third N channel MOS transistors. The drain current of the second and third N channel MOS transistors is output to the drain of the first N channel MOS transistor. An amplitude-current conversion circuit receives the RF signal and provides an output current to the drain of the first N channel MOS transistor to decrease monotonously the output current with respect to the amplitude of the RF signal.Type: ApplicationFiled: March 18, 2005Publication date: September 22, 2005Applicant: Renesas Technology Corp.Inventors: Takaya Maruyama, Hisayasu Sato
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Patent number: 6826393Abstract: A mixer circuit according to the present invention includes a first differential transistor pair of two transistors, a second differential transistor pair of two transistors, an impedance element connected to the first differential transistor pair, an impedance element connected to the second differential transistor pair, an inductor connected to nodes A, B, a current source connected to node A, a current source connected to node B, and a capacitor. A mixer circuit with high conversion gain and small distortion can be obtained.Type: GrantFiled: April 11, 2000Date of Patent: November 30, 2004Assignee: Renesas Technology Corp.Inventors: Hiroshi Komurasaki, Hisayasu Sato, Takahiro Miki
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Publication number: 20040190653Abstract: An initial value register stores gain control amount initial value at the start of a reception frame. At the start of reception frame, a latch unit outputs the value of the gain control amount initial value that has been taken in from initial value register and latched at the end of previous reception frame as a gain control value. A variable gain amplifier amplifies a signal received from mixer in accordance with this initial value. Thereafter, the gain of variable gain amplifier is controlled by a feedback loop structured with an RSSI circuit, a gain control circuit, and a D/A converter circuit, such that the signal level of a reception signal is stabilized at a prescribed level.Type: ApplicationFiled: September 22, 2003Publication date: September 30, 2004Applicant: RENESAS TECHNOLOGY CORP.Inventors: Ikuo Yasui, Hisayasu Sato
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Patent number: 6798678Abstract: There is provided a frequency voltage converter comprises a first transmission line for transmitting an input signal and a second transmission line provided with a delay line circuit, a third transmission line for transmitting a reference signal and a fourth transmission line provided with a delay line circuit, a mixer circuit, and a locked loop having a control circuit for outputting the same control signal to control portions of both delay line circuits so that the amount of a delay by the delay line circuit reaches one cycle of the reference signal, thereby holding linearity with respect to the frequency of a modulated wave signal and executing frequency voltage conversion even when a center frequency is low.Type: GrantFiled: July 9, 2001Date of Patent: September 28, 2004Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Hiroshi Komurasaki, Hisayasu Sato, Takahiro Miki
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Publication number: 20040183606Abstract: An oscillator circuit is formed of a differential LC resonant circuit formed of an L load differential circuit including inductance-variable portions and a capacitor element, and a positive feedback circuit formed of N-channel MOS transistors. The inductance-variable portion is configured to vary the inductance by selecting a plurality of switch circuits arranged between a plurality of arbitrary positions on a spiral interconnection layer and the input/output terminal, and thereby can control an oscillation frequency. The inductance-variable portions form an inductor pair when the switch circuit among the switch circuits coupled between the first input/output terminals is turned on together with the switch circuit.Type: ApplicationFiled: August 21, 2003Publication date: September 23, 2004Applicant: RENESAS TECHNOLOGY CORP.Inventors: Hiroshi Komurasaki, Tomohiro Sano, Hisayasu Sato, Toshio Kumamoto, Yasushi Hashizume
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Patent number: 6639446Abstract: A mixer circuit includes a first signal input terminal connected to the gate of a first MOSFET, and a second signal input terminal connected to the gate of a second MOSFET. The mixer circuit is configured such that a relationship (VG1−VGS2)<(VGS2−VT1) is established, where VG1 is a bias voltage applied to the gate of the first MOS transistor, VGS2 is a bias voltage applied to the gate of the second MOS transistor, and VT1 is a threshold voltage of the first MOS transistor, the bias voltages VG1 and VGS2 being each defined with respect to the source bias voltage of the second MOS transistor. This can implement high linearity mixer circuit even when operated at a low power supply voltage.Type: GrantFiled: July 12, 2002Date of Patent: October 28, 2003Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Hiroshi Komurasaki, Hisayasu Sato, Kimio Ueda
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Publication number: 20030052727Abstract: A mixer circuit includes a first signal input terminal connected to the gate of a first MOSFET, and a second signal input terminal connected to the gate of a second MOSFET. The mixer circuit is configured such that a relationship (VG1−VGS2)<(VGS2−VT1) is established, where VG1 is a bias voltage applied to the gate of the first MOS transistor, VGS2 is a bias voltage applied to the gate of the second MOS transistor, and VT1 is a threshold voltage of the first MOS transistor, the bias voltages VG1 and VGS2 being each defined with respect to the source bias voltage of the second MOS transistor. This can implement high linearity mixer circuit even when operated at a low power supply voltage.Type: ApplicationFiled: July 12, 2002Publication date: March 20, 2003Inventors: Hiroshi Komurasaki, Hisayasu Sato, Kimio Ueda
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Publication number: 20020097592Abstract: There is provided a frequency voltage converter comprises a first transmission line for transmitting an input signal and a second transmission line provided with a delay line circuit, a third transmission line for transmitting a reference signal and a fourth transmission line provided with a delay line circuit, a mixer circuit, and a locked loop having a control circuit for outputting the same control signal to control portions of both delay line circuits so that the amount of a delay by the delay line circuit reaches one cycle of the reference signal, thereby holding linearity with respect to the frequency of a modulated wave signal and executing frequency voltage conversion even when a center frequency is low.Type: ApplicationFiled: July 9, 2001Publication date: July 25, 2002Inventors: Hiroshi Komurasaki, Hisayasu Sato, Takahiro Miki
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Patent number: 6144233Abstract: A gain control circuit includes a first path block for a gain control voltage and a second path block for a reference voltage. The first path block includes a voltage-current linear conversion unit for outputting a current which is proportional to a gain control voltage V.sub.ctrl, and which is inversely proportional to a resistivity, and also includes a temperature characteristic compensation unit for mirroring the current output by the voltage-current linear conversion unit and outputting a current I.sub.ctrl which is proportional to the gain control voltage V.sub.ctrl and an absolute temperature, and which is inversely proportional to the resistivity. The second path block has the same construction as the first path block except that it receives a reference voltage V.sub.ref and outputs a current I.sub.ref. The current I.sub.ctrl and the current I.sub.ref are supplied to a variable- gain cell so as to produce a voltage gain A.sub.v not affected by a variation in temperature.Type: GrantFiled: July 12, 1999Date of Patent: November 7, 2000Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Takaya Maruyama, Hisayasu Sato
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Patent number: 5406136Abstract: The output circuit according to the present invention includes a bipolar transistor (Q.sub.1), a resistance (R.sub.1) and a constant current source. The transistor (Q.sub.1) has its collector connected to a power supply node (V.sub.CC), its emitter connected to an output node (Do), and its base connected to the other end of the resistance (R.sub.1). The resistance (R.sub.1) has one end connected to the power supply node (V.sub.CC). The constant current source is connected between a power supply node (V.sub.EE) and the base of the transistor (Q.sub.1) and is turned on/off in response to an input signal (IN) to generate a current (I.sub.1) for bringing output into a low level only in the on state. The constant current source does not generate the current (I.sub.1) at the time of output of a high level, and causes the current (I.sub.1) to flow through the resistance (R.sub.1) only at the time of output of a low level. As a result, power consumption can be reduced.Type: GrantFiled: May 10, 1993Date of Patent: April 11, 1995Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Harufusa Kondoh, Hisayasu Sato