Abstract: A variable gain amplifier is configured of an amplification circuit and a control circuit controlling a gain of the amplification circuit. The amplification circuit has first and second MOS transistors identical in characteristics and having respective sources connected to a first fixed potential. The amplification circuit has a differential gain proportional to a square root of a ratio between a current flowing through the first MOS transistor and a current flowing through the second MOS transistor. The control circuit applies a potential corresponding to a constant voltage plus a control voltage to a gate of the first MOS transistor and a potential corresponding to the constant voltage minus the control voltage to a gate of the second MOS transistor.

Abstract: A gate electrode has a relatively long gate length of e.g., about 10 &mgr;m. In a region immediately above the gate electrode which is sandwiched between first-layer metals provided is a metal dummy pattern having a width in the first direction and extending in the second direction perpendicular to a direction of gate length (direction of current flow). Moreover, a geometric center of the metal dummy pattern in the second direction is equal to a geometric center of the gate electrode in the second direction. This maintains the symmetry in shape of the metal dummy pattern as viewed from the gate electrode. Such a structure can make deterioration in characteristics of a plurality of elements uniform while maintaining the essential effect of a metal CMP.

Abstract: A differential amplifier of an exponentially-changing current producing circuit has a pair of transistors of which bases are connected to each other through a differential base resistor of a resistance value R, a control current of a value K2×T−(K1×K2×T×Vcont/K3) produced from a gain control current (K1·Vcont), a gain reference current (K3) and a bias current (K2·T) is fed to the base of one transistor, and an exponentially-changing current is output. Vcont denotes a gain control voltage, K1, K2 and K3 are constant, and T denotes an absolute temperature. An input signal is amplified in a variable gain cell at a gain corresponding to the exponentially-changing current, and an amplified signal is output. Therefore, the gain in the variable gain cell is controlled according to the exponentially-changing current.

Abstract: A variable gain amplifier is configured of an amplification circuit and a control circuit controlling a gain of the amplification circuit. The amplification circuit has first and second MOS transistors identical in characteristics and having respective sources connected to a first fixed potential. The amplification circuit has a differential gain proportional to a square root of a ratio between a current flowing through the first MOS transistor and a current flowing through the second MOS transistor. The control circuit applies a potential corresponding to a constant voltage plus a control voltage to a gate of the first MOS transistor and a potential corresponding to the constant voltage minus the control voltage to a gate of the second MOS transistor.

Abstract: A slice circuit includes a DC component adjusting circuit, an integrator, a low pass filter, and a comparator. The DC component adjusting circuit adjusts only a DC component in an input signal sent from an input terminal to produce a DC component having a uniform voltage level. The integrator amplifies only a high frequency component of or above a predetermined frequency in the input signal received from the DC component adjusting circuit. The low pass filter detects an average voltage of the input signal received from the DC component adjusting circuit. The comparator compares a voltage of the output signal sent from the integrator with a voltage of an output signal sent from the low pass filter, and provides a digital signal having a logical level corresponding to results of the comparison to an output terminal.

Abstract: A slice circuit includes a DC component adjusting circuit, an integrator, a low pass filter and a comparator. The DC component adjusting circuit adjusts only a DC component in an input signal sent from an input terminal to produce a DC component formed of a uniform voltage level. The integrator amplifies only a high frequency component of or above a predetermined frequency in the input signal received from the DC component adjusting circuit. The low pass filter detects an average voltage of the input signal received from the DC component adjusting circuit. The comparator compares a voltage of the output signal sent from integrator with a voltage of an output signal sent from the low pass filter, and provides a digital signal having a logical level corresponding to results of the comparison to an output terminal.

Abstract: A semiconductor device is arranged by having a shield/planarization portion including a silicided active region formed on the main surface of a semiconductor substrate and a non-active region provided by device-isolation on the surface, and a metal layer such as a pad, wiring layer or inductor having a predetermined pattern, formed on an interlayer insulation film formed on the above shield/planarization portion. Just under the metal layer is disposed the shield/planarization portion in which the area ratio of the active region to the non-active region is given in a predetermined proportion and the active region is electrically grounded.

Abstract: A semiconductor device is arranged by having a shield/planarization portion including a silicided active region formed on the main surface of a semiconductor substrate and a non-active region provided by device-isolation on the surface, and a metal layer such as a pad, wiring layer or inductor having a predetermined pattern, formed on an interlayer insulation film formed on the above shield/planarization portion. Just under the metal layer is disposed the shield/planarization portion in which the area ratio of the active region to the non-active region is given in a predetermined proportion and the active region is electrically grounded.

Abstract: A differential amplifier of an exponentially-changing current producing circuit has a pair of transistors of which bases are connected to each other through a differential base resistor of a resistance value R, a control current of a value K2×T−(K1×K2×T×Vcont/K3) produced from a gain control current (K1·Vcont) , a gain reference current (K3) and a bias current (K2·T) is fed to the base of one transistor, and an exponentially-changing current is output. Vcont denotes a gain control voltage, K1, K2 and K3 are constant, and T denotes an absolute temperature. An input signal is amplified in a variable gain cell at a gain corresponding to the exponentially-changing current, and an amplified signal is output. Therefore, the gain in the variable gain cell is controlled according to the exponentially-changing current.

Abstract: A gate electrode (1) has a relatively long gate length (L) of e.g., about 10 &mgr;m. In a region immediately above the gate electrode (1) which is sandwiched between first-layer metals (1AL; 4, 5) provided is a metal dummy pattern (6) having a width (W:<L) in the first direction (D1) and extending in the second direction (D2) perpendicular to a direction of gate length (direction of current flow). Moreover, a geometric center of the metal dummy pattern (6) in the second direction (D2) is equal to a geometric center (GC) of the gate electrode (1) in the second direction (D2). This maintains the symmetry in shape of the metal dummy pattern (6) as viewed from the gate electrode (1). Such a structure can make deterioration in characteristics of a plurality of elements uniform while maintaining the essential effect of a metal CMP.

Abstract: A gate electrode has a relatively long gate length of e.g., about 10 &mgr;m. In a region immediately above the gate electrode which is sandwiched between first-layer metals provided is a metal dummy pattern having a width in the first direction and extending in the second direction perpendicular to a direction of gate length (direction of current flow). Moreover, a geometric center of the metal dummy pattern in the second direction is equal to a geometric center of the gate electrode in the second direction. This maintains the symmetry in shape of the metal dummy pattern as viewed from the gate electrode. Such a structure can make deterioration in characteristics of a plurality of elements uniform while maintaining the essential effect of a metal CMP.

Abstract: In a variable frequency divider formed of a latch train, a frequency division ratio is set through selective invalidating a feedback signal to a first stage latch from the last stage latch. A size of MOS (metal-insulator-semiconductor) transistors for switching the division ratio is made larger than that of other MOS transistors in differential stages in the last stage latch circuit. Further, differential signals are transmitted as feedback signals to the first stage latch circuit. A F/(F+1) prescaler which operates stably with a low current consumption under a low power supply voltage condition is implemented.

Abstract: A gate electrode (1) has a relatively long gate length (L) of e.g., about 10 &mgr;m. In a region immediately above the gate electrode (1) which is sandwiched between first-layer metals (1AL; 4, 5) provided is a metal dummy pattern (6) having a width (W:<L) in the first direction (D1) and extending in the second direction (D2) perpendicular to a direction of gate length (direction of current flow). Moreover, a geometric center of the metal dummy pattern (6) in the second direction (D2) is equal to a geometric center (GC) of the gate electrode (1) in the second direction (D2). This maintains the symmetry in shape of the metal dummy pattern (6) as viewed from the gate electrode (1). Such a structure can make deterioration in characteristics of a plurality of elements uniform while maintaining the essential effect of a metal CMP.

Abstract: A mixer circuit having a high conversion gain which is excellent in linearity comprises an amplifier (1A) for amplifying one of two signals to be mixed with each other. The amplifier (1A) comprises a low-pass filter (14) not damping an input voltage (v1) of a frequency (f1) on a negative feedback circuit for its output. Due to the low-pass filter (14), it is possible to reduce harmonics by increasing the feedback amount as the frequency is increased.

Abstract: In a variable frequency divider formed of a latch train, a frequency division ratio is set through selective invalidating a feedback signal to a first stage latch from the last stage latch. A size of MOS (metal-insulator-semiconductor) transistors for switching the division ratio is made larger than that of other MOS transistors in differential stages in the last stage latch circuit. Further, differential signals are transmitted as feedback signals to the first stage latch circuit. A F/(F+1) prescaler which operates stably with a low current consumption under a low power supply voltage condition is implemented.

Abstract: In cases where a direct-current offset occurs in a differential signal output from a differential signal amplifier when a differential input signal is differentially amplified in a series of differential signal amplifiers, a direct-current offset component amplified is included in a differential signal output from a particular differential signal amplifier. To suppress the direct-current offset component, the differential signal is, at first, differentially amplified in a pair of transistors of a detecting amplifier, the direct-current offset component is extracted in a low-pass filter from the differential signal amplified, and compensating currents produced according to the direct-current offset component are input to a differential signal amplifier preceding to the particular differential signal amplifier to adjust the direct-current offset component of the differential signal to zero.

Abstract: An object is to obtain an amplification circuit which provides a high gain even with a low-voltage power supply. The amplification circuit comprises an MOS transistor (M1) having a gate receiving an amplified signal (RFin), a source electrically connected to ground, and a drain electrically connected to a supply voltage (VDD), wherein the back gate-source voltage (Vbs) of the MOS transistor (M1) is made larger as the gate-source voltage (Vgs) of the MOS transistor (M1) becomes larger, thereby making the threshold voltage (VT) of the MOS transistor (M1) smaller.

Abstract: Current controllers (C1 and C2) are connected to a power source (Vcc) in common through a load (L). Inputs of the current controllers (C1 and C2) are connected to outputs of current amplifier parts (A1 and A2) respectively, and the current amplifier parts (A1 and A2) are connected to a ground level (GND) through constant current sources (CS1 and CS2) respectively. The current amplifier part (A1) has a high gain, and the current amplifier part (A2) has a low gain. Thus, a variable gain amplifier whose input range does not abruptly change with respect to a control voltage is obtained, and a variable gain amplifier widening its input range is provided.

Abstract: A phase shifter is provided between common emitters of two differential transistor pairs of a mixer circuit. The phase shifter changes the phase of a voltage signal input to one common emitter by 180.degree. and applies it to the other common emitter, and causes a current in accordance with the voltage between the common emitters. As compared with the prior art employing two stages of vertically connected differential transistor pairs, the power supply voltage can be reduced.

Abstract: First emitters of a pair of input multi-emitter transistors are connected to a current source in common, to form an input differential amplifier. The other emitters of the input multi-emitter transistors are connected to current sources respectively. Pull-up and pull-down transistors are provided for respective ones of a pair of output terminals. Bases of the pull-up transistors are supplied with collector voltages of the input multi-emitter transistors, while those of the pull-down transistors are supplied with voltages of the other emitters of the multi-emitter transistors. Provided is an emitter-coupled logic circuit which has excellent load drivability, operates stably and obtains complementary outputs at a low cost.