Patents by Inventor Hisayuki Maekawa
Hisayuki Maekawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7754572Abstract: A semiconductor device has a semiconductor substrate, a pair of diffusion layers formed in a predetermined regions of the semiconductor substrate, a gate insulation film formed on a region of the semiconductor substrate being interposed between the pair of the diffusion layers, a gate electrode formed on the gate insulation film, insulation films formed on the sides of the gate electrode, each of the insulation films being constructed from one or more layers, sidewall spacers formed on the sides of the gate electrode while the insulation films are interposed between the sidewall spacers and the gate electrode, and highly doped diffusion layers formed in the diffusion layers except for the parts under the insulation films and the sidewall spacers.Type: GrantFiled: September 8, 2005Date of Patent: July 13, 2010Assignee: Oki Semiconductor Co., Ltd.Inventor: Hisayuki Maekawa
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Publication number: 20070212842Abstract: In the manufacturing method of a high-voltage MOS, a structural body is prepared. The structural body includes a semiconductor substrate of a first conductivity type, a gate electrode formed on the semiconductor substrate via a gate insulation film, and first conductive layers of a second conductivity type extending from the surface to the inside of the semiconductor substrate. Main sidewalls are formed on the first conductive layers, and contact whole side surfaces of the gate electrode. Side surfaces of the main sidewalls are perpendicular to the surface of the semiconductor substrate. At least one sub-sidewall is formed on at lest one first conductive layer, and contacts a whole side surface of the main sidewall. Impurities are doped into exposed regions of the first conductive layer through the mask using the gate electrode, the main sidewalls and the sub-sidewall, to thereby form heavily-doped impurity regions of the second conductivity type.Type: ApplicationFiled: October 27, 2006Publication date: September 13, 2007Applicant: OKI ELECTRIC INDUSTRY CO., LTD.Inventor: Hisayuki Maekawa
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Publication number: 20060263948Abstract: A gate oxide film, a gate electrode and low-concentration N type diffusion layers are first formed in a device forming region of a P type silicon substrate. A insulating film is deposited over them and anisotropically etched to form sidewalls. Subsequently, a gate oxide film, a gate electrode and low-concentration N type diffusion layers are formed in a device forming region. An insulating film is deposited over them and anisotropically etched to form sidewalls. The insulating film for the sidewalls and the insulating film for the sidewalls are deposited in discrete processes and the thicknesses of these insulating films are individually adjusted, whereby the widths of the sidewalls can be set to arbitrary values respectively. Thereafter, high-concentration impurity regions are formed on a self-alignment basis by ion implantation.Type: ApplicationFiled: March 7, 2006Publication date: November 23, 2006Inventor: Hisayuki Maekawa
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Publication number: 20060151840Abstract: A semiconductor device has a semiconductor substrate, a pair of diffusion layers formed in a predetermined regions of the semiconductor substrate, a gate insulation film formed on a region of the semiconductor substrate being interposed between the pair of the diffusion layers, a gate electrode formed on the gate insulation film, insulation films formed on the sides of the gate electrode, each of the insulation films being constructed from one or more layers, sidewall spacers formed on the sides of the gate electrode while the insulation films are interposed between the sidewall spacers and the gate electrode, and highly doped diffusion layers formed in the diffusion layers except for the parts under the insulation films and the sidewall spacers.Type: ApplicationFiled: September 8, 2005Publication date: July 13, 2006Applicant: Oki Electric Industry Co., Ltd.Inventor: Hisayuki Maekawa
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Patent number: 6974997Abstract: A high-voltage MOS transistor capable of lowering the maximum substrate current without sacrificing the driving capacity of the transistor itself, and ensuring an acceptable lifetime of hot carriers is provided. By providing an overlapping region in a boundary region between a gate electrode and a lightly doped n-type diffusion layer of a drain electrode, it becomes possible to increase by about 50% a dopant dose of the lightly doped n-type diffusion layer, having effects on the so-called transistor characteristic of the n-channel high-voltage MOS transistor described above. Furthermore, by setting an overlapping amount to not less than 0.5 ?m, it becomes possible to create a stable region with maximum substrate current (Isub max.) at not larger than 5 ?A/?m.Type: GrantFiled: August 6, 2002Date of Patent: December 13, 2005Assignee: Oki Electric Industry Co., Ltd.Inventor: Hisayuki Maekawa
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Publication number: 20030057460Abstract: A high-voltage MOS transistor capable of lowering the maximum substrate current without sacrificing the driving capacity of the transistor itself, and ensuring an acceptable lifetime of hot carriers is provided. By providing an overlapping region in a boundary region between a gate electrode and a lightly doped n-type diffusion layer of a drain electrode, it becomes possible to increase by about 50% a dopant dose of the lightly doped n-type diffusion layer, having effects on the so-called transistor characteristic of the n-channel high-voltage MOS transistor described above. Furthermore, by setting an overlapping amount to not less than 0.5 &mgr;m, it becomes possible to create a stable region with maximum substrate current (Isub max.) at not larger than 5 &mgr;A/&mgr;m.Type: ApplicationFiled: August 6, 2002Publication date: March 27, 2003Inventor: Hisayuki Maekawa
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Patent number: 6163056Abstract: A semiconductor device includes a semiconductor substrate having a major surface, a source region of a second conductivity type, a drain region of the second conductivity type, and a first insulating layer formed over the major surface between the source region and the drain region. The device also includes a control electrode layer formed over the first insulating layer and a second insulating layer formed over the major surface. The device also includes a first wiring layer formed in the first contact hole and a second wiring layer formed in the second contact hole and connected to a pad and an internal circuitry, wherein the internal circuitry executes a predetermined operation and wherein the pad receives a signal from the internal circuitry or a signal from an external device.Type: GrantFiled: June 21, 1999Date of Patent: December 19, 2000Assignee: Oki Electric Industry Co., Ltd.Inventor: Hisayuki Maekawa
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Patent number: 6054743Abstract: A high voltage MOS (Metal Oxide Semiconductor) transistor includes a semiconductor substrate of first conductivity type (P type). A pair of first diffused layers of second conductivity type (N type) are formed on the substrate. A pair of second diffused layers of second conductivity type (N type) are respectively formed in the first diffused layers and have a higher concentration than the first diffused layers. A gate region intervenes between the two first diffused layers facing each other. The gate region consists of a gate oxide film and a gate electrode. The distance between the first diffused layers is smaller in the deep region of the substrate than at the surface of the substrate. The MOS transistor has a great breakdown resisting quantity.Type: GrantFiled: August 14, 1996Date of Patent: April 25, 2000Assignee: Oki Electric Industry Co., Ltd.Inventor: Hisayuki Maekawa