Patents by Inventor Hisayuki Tsuruta

Hisayuki Tsuruta has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6676885
    Abstract: The present invention provides a resin-molding method comprising the steps of: placing a circuit base member onto a mounting face of first one of paired dies, wherein a back face of the circuit base member is in contact with the mounting face; placing the paired dies in a closing state for clamping a peripheral region of the circuit base member with the paired dies; and injecting a molten resin into a cavity of the paired dies for filling the cavity with the injected resin, wherein, in the closing state, a first pressure effected to a front face of the circuit base member is set higher in pressure level than a second pressure effected to the back face of the circuit base member, so as to secure the circuit base member to the mounting face.
    Type: Grant
    Filed: February 12, 2001
    Date of Patent: January 13, 2004
    Assignee: NEC Electronics Corporation
    Inventors: Kazuo Shimizu, Hisayuki Tsuruta
  • Publication number: 20030122279
    Abstract: A mold assembly including: a first mold half; a second mold half relatively movable with respect to the first mold half; and a thin film disposes between the both mold halves and in contact with the surface of a semiconductor chip. Because of the contact between the edges of the surface of the semiconductor chip and the thin film, the portion of the semiconductor chip at which the burr is liable to be generated is protected and no burrs are generated.
    Type: Application
    Filed: February 26, 2003
    Publication date: July 3, 2003
    Applicant: NEC CORPORATION
    Inventor: Hisayuki Tsuruta
  • Patent number: 6554598
    Abstract: A mold assembly including: a first mold half; a second mold half relatively movable with respect to the first mold half; and a thin film disposes between the both mold halves and in contact with the surface of a semiconductor chip. Because of the contact between the edges of the surface of the semiconductor chip and the thin film, the portion of the semiconductor chip at which the burr is liable to be generated is protected and no burrs are generated.
    Type: Grant
    Filed: May 25, 2000
    Date of Patent: April 29, 2003
    Assignee: NEC Electronics Corporation
    Inventor: Hisayuki Tsuruta
  • Patent number: 6315540
    Abstract: A molding die used for concurrently packaging semiconductor chips in a large piece of synthetic resin has a cavity rectangular in cross section and having two long peripheral lines and two short peripheral lines for accommodating a circuit panel where the semiconductor chips are mounted, melted synthetic resin is supplied through a gate extending along one of the long peripheral lines to the cavity so that the melted synthetic resin smoothly flows over the cavity, and the smooth flow prevents the molded product from voids and a wire weep.
    Type: Grant
    Filed: October 6, 2000
    Date of Patent: November 13, 2001
    Assignee: NEC Corporation
    Inventor: Hisayuki Tsuruta
  • Publication number: 20010013674
    Abstract: The present invention provides a resin-molding method comprising the steps of: placing a circuit base member onto a mounting face of first one of paired dies, wherein a back face of the circuit base member is in contact with the mounting face; placing the paired dies in a closing state for clamping a peripheral region of the circuit base member with the paired dies; and injecting a molten resin into a cavity of the paired dies for filling the cavity with the injected resin, wherein, in the closing state, a first pressure effected to a front face of the circuit base member is set higher in pressure level than a second pressure effected to the back face of the circuit base member, so as to secure the circuit base member to the mounting face.
    Type: Application
    Filed: February 12, 2001
    Publication date: August 16, 2001
    Inventors: Kazuo Shimizu, Hisayuki Tsuruta
  • Patent number: 6200121
    Abstract: A molding die used for concurrently packaging semiconductor chips in a large piece of synthetic resin has a cavity rectangular in cross section and having two long peripheral lines and two short peripheral lines for accommodating a circuit panel where the semiconductor chips are mounted, melted synthetic resin is supplied through a gate extending along one of the long peripheral lines to the cavity so that the melted synthetic resin smoothly flows over the cavity, and the smooth flow prevents the molded product from voids and a wire weep.
    Type: Grant
    Filed: June 21, 1999
    Date of Patent: March 13, 2001
    Assignee: NEC Corporation
    Inventor: Hisayuki Tsuruta
  • Patent number: 5357077
    Abstract: The subject is an apparatus for consecutively marking a plurality of packaged semiconductor devices such as ICs by using a laser beam marker. A plurality of packaged semiconductor devices are put into a tubular holder so as to form a single file. The tubular holder is generally rectangular in cross-sectional shape and has a lengthwise opening in the upside wall. The tubular holder is placed on a conveyor belt and secured to the conveyor belt by guide belts each of which makes tight contact with the upside wall or one of the side walls of the tubular holder and advances in the same direction as the conveyor belt. On the conveyor belt the tubular holder passes a marking station where a laser beam is projected on the semiconductor devices in the holder one after another. The apparatus includes a computarized controller to automatically control the positions of the conveyor belt and the guide belts according to the width and height of the tubular holder.
    Type: Grant
    Filed: January 19, 1994
    Date of Patent: October 18, 1994
    Assignee: NEC Corporation
    Inventor: Hisayuki Tsuruta