Patents by Inventor Hisoka Takao

Hisoka Takao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • GaAs MESFET logic buffers using enhancement and depletion FETs
    Patent number: 4707622
    Abstract: A logic circuit includes an inverter circuit including a first enhancement type field effect transistor having a gate connected to an input, and a first depletion type transistor having a gate and a source which are directly connected to a drain of the first enhancement type field effect transistor. A source follower circuit including a second enhancement type field effect transistor having a gate is connected to a connecting point of the first enhancement type field effect transistor and the first depletion type field effect transistor. A second depletion type field effect transistor having a gate and a source which are directly connected to each other has a drain which is connected to a source of the second enhancement type field effect transistor.
    Type: Grant
    Filed: December 31, 1985
    Date of Patent: November 17, 1987
    Assignee: Fujitsu Limited
    Inventors: Hisoka Takao, Toshiro Sato, Seiichi Saito, Toshinari Hayashi