Abstract: A negative voltage decoder applies a negative voltage to the sense line of a selected row of a memory array but not to sense lines of unselected rows. The negative voltage decoder includes a negative voltage source, an array of P-channel transistors, and a negative voltage address signal generator. P-channel transistors in the array have gates coupled to address lines, so that address signals on the address lines turn on the P-channel transistors and connect only the selected sense line to the negative voltage source. A negative voltage charge pumps in the negative voltage address signal generator generates address signals lower than the negative voltage source. In one embodiment, the transistor array has rows of P-channel transistors which fit the pitch of the memory array and individual P-channel transistors which are stacked laterally away from the memory array, and each row of P-channel transistors couples through a set of individual transistor to a set of sense lines.