Patents by Inventor Hitesh Arora

Hitesh Arora has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10472229
    Abstract: A method for fabricating a nanostructure utilizes a templated monocrystalline substrate. The templated monocrystalline substrate is energetically (i.e., preferably thermally) treated, with an optional precleaning and an optional amorphous material layer located thereupon, to form a template structured monocrystalline substrate that includes the monocrystalline substrate with a plurality of epitaxially aligned contiguous monocrystalline pillars extending therefrom. The monocrystalline substrate and the plurality of epitaxially aligned contiguous monocrystalline pillars may comprise the same or different monocrystalline materials.
    Type: Grant
    Filed: March 4, 2011
    Date of Patent: November 12, 2019
    Assignee: Cornell University—Cornell Center for Technology
    Inventors: Ulrich Wiesner, Michael Thompson, Hitesh Arora
  • Patent number: 10347281
    Abstract: Methods are disclosed for increasing areal density in Heat Assisted Magnetic Recording (HAMR) data storage systems by controlling the media layer grain size, grain size distribution, and pitch via templating techniques that are compatible with the high temperature HAMR media deposition. Embodiments include using current HAMR media seed layers as well as additionally introduced interlayers for the templating process. Topographic as well as chemical templating methods are disclosed that may employ nanoimprint technology or nanoparticle self-assembly among other patterning techniques.
    Type: Grant
    Filed: June 2, 2015
    Date of Patent: July 9, 2019
    Assignee: Western Digital Technologies, Inc.
    Inventors: Hitesh Arora, Bruce Gurney, Olav Hellwig, Jodi Mari Iwata, Tiffany Suzanne Santos, Dieter K. Weller, Frank Zhu
  • Patent number: 9719170
    Abstract: Block copolymers (BCPs) and synthetic infiltration synthesis (SIS) are used to double the line density on a substrate. The BCP comprises first and second interconnected BCP components with a functional group at the junction or interface of the components. After deposition of the BCP on the substrate and annealing, a pattern of parallel stripes of first and second BCP components is formed with a pattern of functional group interfaces between the components. Each of the BCP components is non-reactive with atomic layer deposition (ALD) precursors, while the functional group is reactive with the ALD precursors. The ALD results in the infiltration of inorganic material into the interfaces where the reactive functional groups are located but without affecting the BCP components. After removal of the organic material, a pattern of parallel lines of inorganic material remains with a pitch half that of the stripes of BCP components.
    Type: Grant
    Filed: July 12, 2016
    Date of Patent: August 1, 2017
    Assignee: Western Digital Technologies, Inc.
    Inventors: Hitesh Arora, Ricardo Ruiz
  • Patent number: 9640415
    Abstract: Methods for covalently and indelibly anchoring a polyacrylate polymer using a UV-induced polymerization process in the presence of a photoinitiator to an oxide surface are disclosed herein. The methods and compositions prepared by the methods can be used as indelible marking materials for use on microelectronic packages and as solder and sealant barriers to prevent overspreading of liquids on the oxide surfaces of microelectronic packages. The polyacrylate polymers are covalently linked to the oxide surface by use during the printing and UV-curing process of an adhesion promoter having as a first domain an oxide-reactive silyl group, bonded via a linker to an acrylate-reactive group.
    Type: Grant
    Filed: December 1, 2014
    Date of Patent: May 2, 2017
    Assignee: Intel Corporation
    Inventors: Randall D Lowe, Jr., Suriyakala Suriya Ramalingam, Nisha Ananthakrishnan, James C. Matayabas, Jr., Arjun Krishnan, Hitesh Arora
  • Patent number: 9530718
    Abstract: A die backside film including a matrix material; and an amount of filler particles to render the die backside film thermally conductive, wherein a thermal conductivity of the amount of filler particles is greater than a thermal conductivity of silica particles. A method including introducing a die backside film on a backside surface of a die, the die backside film including a matrix material including an elastomer an amount of filler particles to render the die backside film thermally conductive, wherein a thermal conductivity of the amount of filler particles is greater than a thermal conductivity of silica particles; and disposing the die in a package.
    Type: Grant
    Filed: December 26, 2012
    Date of Patent: December 27, 2016
    Assignee: Intel Corporation
    Inventors: Hitesh Arora, Mihir A. Oka, Chandra M. Jha
  • Publication number: 20160358622
    Abstract: Methods are disclosed for increasing areal density in Heat Assisted Magnetic Recording (HAMR) data storage systems by controlling the media layer grain size, grain size distribution, and pitch via templating techniques that are compatible with the high temperature HAMR media deposition. Embodiments include using current HAMR media seed layers as well as additionally introduced interlayers for the templating process. Topographic as well as chemical templating methods are disclosed that may employ nanoimprint technology or nanoparticle self-assembly among other patterning techniques.
    Type: Application
    Filed: June 2, 2015
    Publication date: December 8, 2016
    Inventors: Hitesh Arora, Bruce GURNEY, Olav HELLWIG, Jodi Mari IWATA, Tiffany Suzanne SANTOS, Dieter K. WELLER, Frank ZHU
  • Publication number: 20160343591
    Abstract: Embodiments of the present disclosure are directed to techniques and configurations for an integrated circuit (IC) package having an underfill layer with filler particles arranged in a generally random distribution pattern. In some embodiments, a generally random distribution pattern of filler particles may be obtained by reducing an electrostatic charge on one or more components of the IC package assembly, by applying a surface treatment to filler to reduce filler electrical charge, by applying an electric force against the filler particles of the underfill material in a direction opposite to a direction of gravitational force, by using an underfill material with a relatively low maximum filler particle size, and/or by snap curing the underfill layer at a relatively low temperature. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: August 1, 2016
    Publication date: November 24, 2016
    Inventors: Suriyakala Ramalingam, Manish Dubey, Hsin-Yu Li, Michelle S. Phen-Givoni, Hitesh Arora, Nisha Ananthakrishnan, Yiqun Bai, Yonghao Xiu, Rajendra C. Dias
  • Publication number: 20160319427
    Abstract: Block copolymers (BCPs) and synthetic infiltration synthesis (SIS) are used to double the line density on a substrate. The BCP comprises first and second interconnected BCP components with a functional group at the junction or interface of the components. After deposition of the BCP on the substrate and annealing, a pattern of parallel stripes of first and second BCP components is formed with a pattern of functional group interfaces between the components. Each of the BCP components is non-reactive with atomic layer deposition (ALD) precursors, while the functional group is reactive with the ALD precursors. The ALD results in the infiltration of inorganic material into the interfaces where the reactive functional groups are located but without affecting the BCP components. After removal of the organic material, a pattern of parallel lines of inorganic material remains with a pitch half that of the stripes of BCP components.
    Type: Application
    Filed: July 12, 2016
    Publication date: November 3, 2016
    Inventors: Hitesh Arora, Ricardo Ruiz
  • Patent number: 9464348
    Abstract: A method for making a bit-patterned media (BPM) magnetic recording disk by etching the recording layer using a patterned hard mask layer uses glancing angle deposition (GLAD) of additional hard mask material as a capping layer onto the tops of the patterned hard mask pillars while the disk is rotated about an axis orthogonal to the plane of the disk. In one embodiment the capping layer is deposited after the pillars have been only partially eroded during a partial ion-milling of the recording layer. Ion-milling is then again performed to remove the remaining recording layer material. In another embodiment, before ion-milling of the recording layer, the capping layer is deposited onto the tops of the un-eroded hard mask pillars. This increases the lateral dimension of the hard mask pillars so that after ion-milling of the recording layer, the magnetic islands have an increased lateral dimension.
    Type: Grant
    Filed: August 26, 2014
    Date of Patent: October 11, 2016
    Assignee: HGST Netherlands B.V.
    Inventors: Hitesh Arora, Jean-Marc L. Beaujour, Zuwei Liu, Tsai-Wei Wu
  • Patent number: 9431046
    Abstract: A perpendicular magnetic recording (PMR) disk has a patterned template layer for the growth of the magnetic grains and the nonmagnetic material surrounding the grains. The template layer is a substantially planar platinum (Pt) or palladium (Pd) layer that is patterned to have Pt or Pd regions arranged in a hexagonal-close-packed (hcp) pattern with the Pt or Pd regions surrounded by Pt-oxide or Pd-oxide regions. The two separate regions of the template layer have different surface chemistries and energies, which provide a “chemical contrast” to impinging atoms during deposition of the metallic magnetic material and nonmagnetic (typically oxide) material, effectively guiding the deposition. The metallic magnetic material is preferentially deposited on the pristine, epitaxial Pt or Pd regions to form the magnetic grains, while the oxide migrates to the oxidized Pt or Pd regions due to the matching of lower surface energy.
    Type: Grant
    Filed: October 31, 2014
    Date of Patent: August 30, 2016
    Assignee: HGST Netherlands B.V.
    Inventors: Hitesh Arora, Andrea Fasoli, Qing Zhu
  • Patent number: 9431274
    Abstract: Embodiments of the present disclosure are directed to techniques and configurations for an integrated circuit (IC) package having an underfill layer with filler particles arranged in a generally random distribution pattern. In some embodiments, a generally random distribution pattern of filler particles may be obtained by reducing an electrostatic charge on one or more components of the IC package assembly, by applying a surface treatment to filler to reduce filler electrical charge, by applying an electric force against the filler particles of the underfill material in a direction opposite to a direction of gravitational force, by using an underfill material with a relatively low maximum filler particle size, and/or by snap curing the underfill layer at a relatively low temperature. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: December 20, 2012
    Date of Patent: August 30, 2016
    Assignee: Intel Corporation
    Inventors: Suriyakala Ramalingam, Manish Dubey, Hsin-Yu Li, Michelle S. Phen, Hitesh Arora, Nisha Ananthakrishnan, Yiqun Bai, Yonghao Xiu, Rajendra C. Dias
  • Patent number: 9416447
    Abstract: Block copolymers (BCPs) and synthetic infiltration synthesis (SIS) are used to double the line density on a substrate. The BCP comprises first and second interconnected BCP components with a functional group at the junction or interface of the components. After deposition of the BCP on the substrate and annealing, a pattern of parallel stripes of first and second BCP components is formed with a pattern of functional group interfaces between the components. Each of the BCP components is non-reactive with atomic layer deposition (ALD) precursors, while the functional group is reactive with the ALD precursors. The ALD results in the infiltration of inorganic material into the interfaces where the reactive functional groups are located but without affecting the BCP components. After removal of the organic material, a pattern of parallel lines of inorganic material remains with a pitch half that of the stripes of BCP components.
    Type: Grant
    Filed: February 7, 2014
    Date of Patent: August 16, 2016
    Assignee: HGST Netherlands B.V.
    Inventors: Hitesh Arora, Ricardo Ruiz
  • Patent number: 9336809
    Abstract: A method to fabricate an imprint template for bit-patterned magnetic recording media using block copolymers (BCPs) integrates data region patterning and servo region patterning. A heat sink layer is formed on the imprint substrate only in the data regions. A sublayer for the BCP is deposited over both the data regions and the servo regions and patterned to form stripes in the data regions and servo features in the servo regions. A BCP is then deposited in both the data and servo regions. Only the BCP in the data regions is heated, which causes phase separation of the BCP in the data regions into the two BCP components. The selective heating may be accomplished by directed controlled laser radiation to only the data regions. The heat sink layer below the data regions absorbs the heat from the laser radiation, confining it to the data regions.
    Type: Grant
    Filed: August 28, 2014
    Date of Patent: May 10, 2016
    Assignee: HGST Netherlands B.V.
    Inventors: Hitesh Arora, Sripathi Vangipuram Canchi, Franck Dreyfus Rose, Ricardo Ruiz, Vipin Ayanoor-Vitikkate
  • Publication number: 20160125904
    Abstract: A perpendicular magnetic recording (PMR) disk has a patterned template layer for the growth of the magnetic grains and the nonmagnetic material surrounding the grains. The template layer is a substantially planar platinum (Pt) or palladium (Pd) layer that is patterned to have Pt or Pd regions arranged in a hexagonal-close-packed (hcp) pattern with the Pt or Pd regions surrounded by Pt-oxide or Pd-oxide regions. The two separate regions of the template layer have different surface chemistries and energies, which provide a “chemical contrast” to impinging atoms during deposition of the metallic magnetic material and nonmagnetic (typically oxide) material, effectively guiding the deposition. The metallic magnetic material is preferentially deposited on the pristine, epitaxial Pt or Pd regions to form the magnetic grains, while the oxide migrates to the oxidized Pt or Pd regions due to the matching of lower surface energy.
    Type: Application
    Filed: October 31, 2014
    Publication date: May 5, 2016
    Inventors: Hitesh Arora, Andrea Fasoli, Qing Zhu
  • Publication number: 20160064026
    Abstract: A method for making a bit-patterned media (BPM) magnetic recording disk by etching the recording layer using a patterned hard mask layer uses glancing angle deposition (GLAD) of additional hard mask material as a capping layer onto the tops of the patterned hard mask pillars while the disk is rotated about an axis orthogonal to the plane of the disk. In one embodiment the capping layer is deposited after the pillars have been only partially eroded during a partial ion-milling of the recording layer. Ion-milling is then again performed to remove the remaining recording layer material. In another embodiment, before ion-milling of the recording layer, the capping layer is deposited onto the tops of the un-eroded hard mask pillars. This increases the lateral dimension of the hard mask pillars so that after ion-milling of the recording layer, the magnetic islands have an increased lateral dimension.
    Type: Application
    Filed: August 26, 2014
    Publication date: March 3, 2016
    Inventors: Hitesh Arora, Jean-Marc L. Beaujour, Zuwei Liu, Tsai-Wei Wu
  • Publication number: 20160064027
    Abstract: A method to fabricate an imprint template for bit-patterned magnetic recording media using block copolymers (BCPs) integrates data region patterning and servo region patterning. A heat sink layer is formed on the imprint substrate only in the data regions. A sublayer for the BCP is deposited over both the data regions and the servo regions and patterned to form stripes in the data regions and servo features in the servo regions. A BCP is then deposited in both the data and servo regions. Only the BCP in the data regions is heated, which causes phase separation of the BCP in the data regions into the two BCP components. The selective heating may be accomplished by directed controlled laser radiation to only the data regions. The heat sink layer below the data regions absorbs the heat from the laser radiation, confining it to the data regions.
    Type: Application
    Filed: August 28, 2014
    Publication date: March 3, 2016
    Inventors: Hitesh Arora, Sripathi Vangipuram Canchi, Franck Dreyfus Rose, Ricardo Ruiz, Vipin Ayanoor-Vitikkate
  • Publication number: 20150287901
    Abstract: Thermoelectric structures include a flexible substrate; a plurality of conductive shunts; and a plurality of thermoelectric legs that are in thermal and electrical communication with the thermoelectric legs via thermal and electrical paths. In some embodiments, the paths are through apertures in the flexible substrate, and the flexible substrate can be substantially out of the thermal and electrical paths. Some embodiments include a circuit board coupled to the flexible substrate, and a bend in the flexible substrate can be disposed between the plurality of conductive shunts and the circuit board. In some embodiments, a plurality of perforations are defined through the flexible substrate and can be configured to rupture responsive to a temperature condition that otherwise would damage one or more of the thermal and electrical paths, said rupture inhibiting such damage. Other embodiments, and methods, are provided.
    Type: Application
    Filed: April 6, 2015
    Publication date: October 8, 2015
    Inventors: Adam Lorimer, Jordan Chase, Sasi Bhushan Beera, Mario Aguirre, Hitesh Arora, Douglas Crane
  • Publication number: 20150225850
    Abstract: Block copolymers (BCPs) and synthetic infiltration synthesis (SIS) are used to double the line density on a substrate. The BCP comprises first and second interconnected BCP components with a functional group at the junction or interface of the components. After deposition of the BCP on the substrate and annealing, a pattern of parallel stripes of first and second BCP components is formed with a pattern of functional group interfaces between the components. Each of the BCP components is non-reactive with atomic layer deposition (ALD) precursors, while the functional group is reactive with the ALD precursors. The ALD results in the infiltration of inorganic material into the interfaces where the reactive functional groups are located but without affecting the BCP components. After removal of the organic material, a pattern of parallel lines of inorganic material remains with a pitch half that of the stripes of BCP components.
    Type: Application
    Filed: February 7, 2014
    Publication date: August 13, 2015
    Applicant: HGST Netherlands B.V.
    Inventors: Hitesh Arora, Ricardo Ruiz
  • Publication number: 20150166804
    Abstract: Methods for covalently and indelibly anchoring a polyacrylate polymer using a UV-induced polymerization process in the presence of a photoinitiator to an oxide surface are disclosed herein. The methods and compositions prepared by the methods can be used as indelible marking materials for use on microelectronic packages and as solder and sealant barriers to prevent overspreading of liquids on the oxide surfaces of microelectronic packages. The polyacrylate polymers are covalently linked to the oxide surface by use during the printing and UV-curing process of an adhesion promoter having as a first domain an oxide-reactive silyl group, bonded via a linker to an acrylate-reactive group.
    Type: Application
    Filed: December 1, 2014
    Publication date: June 18, 2015
    Inventors: Randall D. Lowe, JR., Suriyakala Suriya Ramalingam, Nisha Ananthakrishnan, James C. Matayabas, JR., Arjun Krishnan, Hitesh Arora
  • Patent number: 8920919
    Abstract: Certain embodiments relate to compositions that may be used as thermal interface materials in electronic assemblies. One such composition includes a block copolymer matrix comprising polystyrene and polybutene. The composition also includes a filler positioned in the copolymer matrix, the filler comprising carbon. The filler may in certain embodiments be a material selected from the group consisting of graphite, graphene, and carbon nanotubes. composition may include routing structures and their formation. Assemblies may include the composition positioned between a die and a heat spreader. Other embodiments are described and claimed.
    Type: Grant
    Filed: September 24, 2012
    Date of Patent: December 30, 2014
    Assignee: Intel Corporation
    Inventors: Hitesh Arora, James C. Matayabas, Jr.