Patents by Inventor Hitesh Golechchha

Hitesh Golechchha has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11347420
    Abstract: Aspects of a multi-protocol storage device including a memory and a controller are provided which allow for endurance and other storage requirements of a host to be maintained for different logical regions of memory without disruption due to protocol switching. The memory includes blocks that are each associated with a storage attribute such as high endurance, performance, or protection. While operating in a first mode such as NVMe, the controller receives a mapping of storage attributes to different logical regions and stores the mapping in memory. The controller also associates blocks to logical addresses based on the mapping. When the controller switches to a second mode such as SD in response to a host command, the controller reads the mapping from memory and similarly associates blocks to logical addresses based on the mapping in the second mode. Storage attributes thus remain applicable across modes when mapping and storing data.
    Type: Grant
    Filed: June 8, 2020
    Date of Patent: May 31, 2022
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Ramanathan Muthiah, Dinesh Kumar Agarwal, Hitesh Golechchha
  • Patent number: 11314445
    Abstract: Aspects of a storage device are provided which allow for identification of control page patterns from previous read commands and prediction of control pages to load in advance for subsequent read commands. The storage device includes a memory configured to store data and a plurality of control pages. Each of the control pages includes a plurality of logical addresses associated with the data. A controller is configured to receive from a host device a plurality of read commands associated with a sequence of the control pages. The controller is further configured to identify and store a control page pattern based on the sequence of control pages and to predict one or more of the control pages from one or more of the other control pages in the sequence in a subsequent plurality of read commands.
    Type: Grant
    Filed: November 19, 2019
    Date of Patent: April 26, 2022
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Dinesh Kumar Agarwal, Hitesh Golechchha, Sourabh Sankule
  • Patent number: 11294579
    Abstract: Aspects of a multi-protocol storage device including a controller are provided which handle mode switches after a shutdown resulting in a large amount of unfinished work by phasing the work during and after initialization. The controller operates in a first mode such as an SD mode and a second mode such as a NVMe mode. In the event of a shutdown in the second mode resulting in unfinished work, the controller initializes in the first mode. During initialization, the controller determines whether a completion time for the unfinished work exceeds an initialization time in the first mode. When the completion time exceeds the initialization time, the controller performs a first portion of the work during initialization and postpones performance of at least a second portion of the unfinished work until after initialization. As a result, initialization timeouts in the first mode due to the unfinished work may be avoided.
    Type: Grant
    Filed: June 18, 2020
    Date of Patent: April 5, 2022
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Ramanathan Muthiah, Hitesh Golechchha, Dinesh Kumar Agarwal
  • Patent number: 11287989
    Abstract: A system, apparatus, and method for dynamic allocation of sub-blocks. First, a non-volatile memory array receives a set of write commands. The non-volatile memory array comprises multiple memory dies organized into metablocks. The metablocks are configured to span two or more memory dies. A stream manager determines a workload type for the set of write commands. A block allocation manager selects a target storage block to receive the set of write commands based on the workload type. The selected target storage block is configured to receive data blocks for the workload type and the block allocation manager directs the set of write commands to the target storage block.
    Type: Grant
    Filed: March 24, 2020
    Date of Patent: March 29, 2022
    Assignee: Western Digital Technologies, Inc.
    Inventors: Shivam Mishra, Hitesh Golechchha, Shakti Bhatnagar
  • Publication number: 20210397352
    Abstract: Aspects of a multi-protocol storage device including a controller are provided which handle mode switches after a shutdown resulting in a large amount of unfinished work by phasing the work during and after initialization. The controller operates in a first mode such as an SD mode and a second mode such as a NVMe mode. In the event of a shutdown in the second mode resulting in unfinished work, the controller initializes in the first mode. During initialization, the controller determines whether a completion time for the unfinished work exceeds an initialization time in the first mode. When the completion time exceeds the initialization time, the controller performs a first portion of the work during initialization and postpones performance of at least a second portion of the unfinished work until after initialization. As a result, initialization timeouts in the first mode due to the unfinished work may be avoided.
    Type: Application
    Filed: June 18, 2020
    Publication date: December 23, 2021
    Inventors: Ramanathan Muthiah, Hitesh Golechchha, Dinesh Kumar Agarwal
  • Publication number: 20210382621
    Abstract: Aspects of a multi-protocol storage device including a memory and a controller are provided which allow for endurance and other storage requirements of a host to be maintained for different logical regions of memory without disruption due to protocol switching. The memory includes blocks that are each associated with a storage attribute such as high endurance, performance, or protection. While operating in a first mode such as NVMe, the controller receives a mapping of storage attributes to different logical regions and stores the mapping in memory. The controller also associates blocks to logical addresses based on the mapping. When the controller switches to a second mode such as SD in response to a host command, the controller reads the mapping from memory and similarly associates blocks to logical addresses based on the mapping in the second mode. Storage attributes thus remain applicable across modes when mapping and storing data.
    Type: Application
    Filed: June 8, 2020
    Publication date: December 9, 2021
    Inventors: Ramanathan Muthiah, Dinesh Kumar Agarwal, Hitesh Golechchha
  • Publication number: 20210326172
    Abstract: A storage system and method for multiprotocol handling are provided. In one embodiment, a computing device is provided comprising a plurality of communication channels configured to communicate with a storage system, wherein a first communication channel has a faster data transfer speed than a second communication channel. The computing device also comprises a processor configured to determine a priority level of a command; send the command with an indication of its priority level to the storage system; in response to the command being a high-priority command, use the first communication channel for transferring data for the command; and in response to the command being a low-priority command, use the second communication channel for transferring data for the command. Other embodiments are provided.
    Type: Application
    Filed: April 17, 2020
    Publication date: October 21, 2021
    Applicant: Western Digital Technologies, Inc.
    Inventors: Ramanathan Muthiah, Hitesh Golechchha, Dinesh Kumar Agarwal
  • Publication number: 20210303185
    Abstract: A system, apparatus, and method for dynamic allocation of sub-blocks. First, a non-volatile memory array receives a set of write commands. The non-volatile memory array comprises multiple memory dies organized into metablocks. The metablocks are configured to span two or more memory dies. A stream manager determines a workload type for the set of write commands. A block allocation manager selects a target storage block to receive the set of write commands based on the workload type. The selected target storage block is configured to receive data blocks for the workload type and the block allocation manager directs the set of write commands to the target storage block.
    Type: Application
    Filed: March 24, 2020
    Publication date: September 30, 2021
    Applicant: Western Digital Technologies, Inc.
    Inventors: Shivam Mishra, Hitesh Golechchha, Shakti Bhatnagar
  • Publication number: 20210149583
    Abstract: Aspects of a storage device are provided which allow for identification of control page patterns from previous read commands and prediction of control pages to load in advance for subsequent read commands. The storage device includes a memory configured to store data and a plurality of control pages. Each of the control pages includes a plurality of logical addresses associated with the data. A controller is configured to receive from a host device a plurality of read commands associated with a sequence of the control pages. The controller is further configured to identify and store a control page pattern based on the sequence of control pages and to predict one or more of the control pages from one or more of the other control pages in the sequence in a subsequent plurality of read commands.
    Type: Application
    Filed: November 19, 2019
    Publication date: May 20, 2021
    Inventors: Dinesh Kumar Agarwal, Hitesh Golechchha, Sourabh Sankule
  • Patent number: 10963592
    Abstract: A memory device operable in either of a Secure Digital operational mode and an NVMe operational mode includes password conversion logic to enable the memory device user-mode memory blocks to be accessed in the NVMe operational mode after the memory device was locked in the Secure Digital operational mode.
    Type: Grant
    Filed: February 5, 2019
    Date of Patent: March 30, 2021
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Vinod Sasidharan, Hitesh Golechchha, Dinesh Kumar Agarwal
  • Patent number: 10832790
    Abstract: A storage device may include a controller performing non data word line (NDWL) maintenance in sub block mode (SBM). The NDWL maintenance in SBM can include proactive select gate drain (SGD) detection and phased SGD correction. For example, when a block reaches a PE cycle threshold value, SGD phased correction occurs upon detection of an error, by determining whether a sister sub block of the selected block contains data. If the sister sub block contains data, the data is transferred from the sister sub block, and then the block and sister sub block undergo correction for NDLW maintenance.
    Type: Grant
    Filed: September 26, 2019
    Date of Patent: November 10, 2020
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Shakti Bhatnagar, Shivam Mishra, Hitesh Golechchha
  • Publication number: 20200250346
    Abstract: A memory device operable in either of a Secure Digital operational mode and an NVMe operational mode includes password conversion logic to enable the memory device user-mode memory blocks to be accessed in the NVMe operational mode after the memory device was locked in the Secure Digital operational mode.
    Type: Application
    Filed: February 5, 2019
    Publication date: August 6, 2020
    Inventors: Vinod Sasidharan, Hitesh Golechchha, Dinesh Kumar Agarwal
  • Patent number: 10209914
    Abstract: A system and method for managing data writes in a non-volatile memory including SLC and MLC blocks of non-volatile memory and a MLC block health rating data structure tracking relative MLC block health. A controller in the system may be configured to select MLC blocks for receiving host data and then route the host data over a direct MLC write path for healthy blocks, or over a two-step indirect write path that includes a SLC write and a SLC-MLC fold for unhealthy MLC blocks. The method may include assigning a health designation based on BER determined for each MLC block and assigning a direct write number to healthy MLC blocks based on the determined BER that limits the number of program/erase cycles for direct writes for a particular MLC block until a re-assessment of block health is needed.
    Type: Grant
    Filed: January 31, 2017
    Date of Patent: February 19, 2019
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Dinesh Agarwal, Hitesh Golechchha, Guruswamy Ganesh
  • Patent number: 10153046
    Abstract: A memory system comprises a plurality of non-volatile memory cells grouped into blocks of memory cells and a control circuit in communication with the memory cells. The control circuit is configured to program original data to a first block of memory cells and backup the original data by programming a copy of the original data across multiple blocks of memory cells at a word line offset. After being used to store backups of original data, blocks are rotated to be used for storing original data.
    Type: Grant
    Filed: October 30, 2017
    Date of Patent: December 11, 2018
    Assignee: Western DigitalTechnologies, Inc.
    Inventors: Dinesh Agarwal, Hitesh Golechchha
  • Publication number: 20180217751
    Abstract: A system and method is disclosed for managing data writes in a non-volatile memory. The system may include a non-volatile memory having SLC and MLC blocks of non-volatile memory and a MLC block health rating data structure tracking relative MLC block health. A controller in the system may be configured to select MLC blocks for receiving host data and then route the host data over a direct MLC write path for healthy blocks, or over a two-step indirect write path that includes a SLC write and a SLC-MLC fold for unhealthy MLC blocks. The method may include assigning a health designation based on BER determined for each MLC block and assigning a direct write number to healthy MLC blocks based on the determined BER that limits the number of program/erase cycles for direct writes for a particular MLC block until a re-assessment of block health is needed.
    Type: Application
    Filed: January 31, 2017
    Publication date: August 2, 2018
    Applicant: SanDisk Technologies LLC
    Inventors: Dinesh Agarwal, Hitesh Golechchha, Guruswamay Ganesh