Abstract: A method and system for an IC design house to transfer design and layout information to a fabrication or failure analysis facility on a need-to-know basis to enable effective failure analysis while not providing unnecessary or extraneous information.

Abstract: Enhanced algorithms are provided for finding circuit edit locations which utilize automated conversions from circuit schematic to physical layout design. The enhanced algorithms further include a user interface enabling the user to provide preferences, limitations, and constraints in order to bias the search to be conducted, as well as using the provided design data in order to locate the best positions for particular edit schemes, including net cuts and net joins.

Abstract: A method and system for an IC design house to transfer design and layout information to a fabrication or failure analysis facility on a need-to-know basis to enable effective failure analysis while not providing unnecessary or extraneous information.

Abstract: A method and apparatus for optimizing an integrated circuit design for post-fabrication circuit editing and diagnostics. The method and apparatus is specifically directed to adding designed-for-edit modifications and designed-for-diagnostics structures to an integrated circuit design for post-fabrication circuit editing with a charged-particle beam tool. An integrated circuit design may be modified to create efficient and reliable access to specified nodes and structures, such as spare gates, by the charged-particle beam tool during subsequent testing and debugging of the fabricated device. Additionally, structures such as spare gates, spare transistors, spare metal wires, and debug circuitry may be added to an integrated circuit design to provide for easier editing of portions of the design that may fail.

Abstract: Enhanced algorithms are provided for finding circuit edit locations which utilize automated conversions from circuit schematic to physical layout design. The enhanced algorithms further include a user interface enabling the user to provide preferences, limitations, and constraints in order to bias the search to be conducted, as well as using the provided design data in order to locate the best positions for particular edit schemes, including net cuts and net joins.

Abstract: An apparatus and method for tracing back a probing location to identify the circuit element being probed on a device under test (DUT). The coordinates of the irregularity on the DUT are used to trace back to the logic cone to decipher the root-cause of the irregularity. The Def and Lef files are interrogated using the coordinates to obtain the cell and net data to enable the investigation. Additionally, a schematic viewer is used to investigate the logic cone to potential root-causes for the irregularities.

Abstract: A method for identifying an area of a chip to be probed proceeds as follows. A callout list of failures is obtained from a tester, the list including cell name and pin for each failure. A Def file is interrogated to locate a Def entry matching the cell name, and a cell type, cell location, and cell orientation data is obtained for the cell from the Def file. A Lef file is then interrogated to locate a Lef entry matching the cell type, and the coordinates of the pin are obtaining from the Lef file. A GDS file is interrogated to locate a GDS entry matching the cell type, and the coordinates of polygons listed in the GDS entry are obtained. The coordinates of the pin are then crossed with the coordinates of the polygons to identify overlapping area. The overlapping area is defined as the location to be probed. A driving signal is applied to a stage to align a prober with the location to be rprobed.

Abstract: An apparatus and method for tracing back a probing location to identify the circuit element being probed on a device under test (DUT). The coordinates of the irregularity on the DUT are used to trace back to the logic cone to decipher the root-cause of the irregularity. The Def and Lef files are interrogated using the coordinates to obtain the cell and net data to enable the investigation. Additionally, a schematic viewer is used to investigate the logic cone to potential root-causes for the irregularities.

Abstract: A method for identifying an area of a chip to be probed proceeds as follows. A callout list of failures is obtained from a tester, the list including cell name and pin for each failure. A Def file is interrogated to locate a Def entry matching the cell name, and a cell type, cell location, and cell orientation data is obtained for the cell from the Def file. A Lef file is then interrogated to locate a Lef entry matching the cell type, and the coordinates of the pin are obtaining from the Lef file. A GDS file is interrogated to locate a GDS entry matching the cell type, and the coordinates of polygons listed in the GDS entry are obtained. The coordinates of the pin are then crossed with the coordinates of the polygons to identify overlapping area. The overlapping area is defined as the location to be probed. A driving signal is applied to a stage to align a prober with the location to be probed.